30 	case 0x00e0:  in rt1308_readable_register()
31 	case 0x00f0:  in rt1308_readable_register()
32 	case 0x2f01 ... 0x2f07:  in rt1308_readable_register()
33 	case 0x3000 ... 0x3001:  in rt1308_readable_register()
34 	case 0x3004 ... 0x3005:  in rt1308_readable_register()
35 	case 0x3008:  in rt1308_readable_register()
36 	case 0x300a:  in rt1308_readable_register()
37 	case 0xc000 ... 0xcff3:  in rt1308_readable_register()
47 	case 0x2f01 ... 0x2f07:  in rt1308_volatile_register()
48 	case 0x3000 ... 0x3001:  in rt1308_volatile_register()
49 	case 0x3004 ... 0x3005:  in rt1308_volatile_register()
50 	case 0x3008:  in rt1308_volatile_register()
51 	case 0x300a:  in rt1308_volatile_register()
52 	case 0xc000:  in rt1308_volatile_register()
64 	.max_register = 0xcfff,
89 		value = 0x0;  in rt1308_clock_config()
92 		value = 0x1;  in rt1308_clock_config()
95 		value = 0x2;  in rt1308_clock_config()
98 		value = 0x3;  in rt1308_clock_config()
101 		value = 0x4;  in rt1308_clock_config()
104 		value = 0x5;  in rt1308_clock_config()
110 	regmap_write(rt1308->regmap, 0xe0, value);  in rt1308_clock_config()
111 	regmap_write(rt1308->regmap, 0xf0, value);  in rt1308_clock_config()
115 	return 0;  in rt1308_clock_config()
132 	prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */  in rt1308_read_prop()
133 	prop->sink_ports = 0x2; /* BITMAP:  00000010 */  in rt1308_read_prop()
143 	i = 0;  in rt1308_read_prop()
159 	return 0;  in rt1308_read_prop()
165 	int ret = 0;  in rt1308_io_init()
170 		return 0;  in rt1308_io_init()
197 	regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);  in rt1308_io_init()
200 	regmap_write(rt1308->regmap, 0xc360, 0x01);  in rt1308_io_init()
201 	regmap_write(rt1308->regmap, 0xc361, 0x80);  in rt1308_io_init()
202 	regmap_write(rt1308->regmap, 0xc7f0, 0x04);  in rt1308_io_init()
203 	regmap_write(rt1308->regmap, 0xc7f1, 0xfe);  in rt1308_io_init()
205 	regmap_write(rt1308->regmap, 0xc7f0, 0x44);  in rt1308_io_init()
207 	regmap_write(rt1308->regmap, 0xc240, 0x10);  in rt1308_io_init()
209 	regmap_read(rt1308->regmap, 0xc861, &tmp);  in rt1308_io_init()
211 	regmap_read(rt1308->regmap, 0xc860, &tmp);  in rt1308_io_init()
213 	regmap_read(rt1308->regmap, 0xc863, &tmp);  in rt1308_io_init()
215 	regmap_read(rt1308->regmap, 0xc862, &tmp);  in rt1308_io_init()
217 	regmap_read(rt1308->regmap, 0xc871, &tmp);  in rt1308_io_init()
219 	regmap_read(rt1308->regmap, 0xc870, &tmp);  in rt1308_io_init()
221 	regmap_read(rt1308->regmap, 0xc873, &tmp);  in rt1308_io_init()
223 	regmap_read(rt1308->regmap, 0xc872, &tmp);  in rt1308_io_init()
225 	dev_dbg(&slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__,  in rt1308_io_init()
227 	dev_dbg(&slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__,  in rt1308_io_init()
231 	regmap_write(rt1308->regmap, 0xc103, 0xc0);  in rt1308_io_init()
232 	regmap_write(rt1308->regmap, 0xc030, 0x17);  in rt1308_io_init()
233 	regmap_write(rt1308->regmap, 0xc031, 0x81);  in rt1308_io_init()
234 	regmap_write(rt1308->regmap, 0xc032, 0x26);  in rt1308_io_init()
235 	regmap_write(rt1308->regmap, 0xc040, 0x80);  in rt1308_io_init()
236 	regmap_write(rt1308->regmap, 0xc041, 0x80);  in rt1308_io_init()
237 	regmap_write(rt1308->regmap, 0xc042, 0x06);  in rt1308_io_init()
238 	regmap_write(rt1308->regmap, 0xc052, 0x0a);  in rt1308_io_init()
239 	regmap_write(rt1308->regmap, 0xc080, 0x0a);  in rt1308_io_init()
240 	regmap_write(rt1308->regmap, 0xc060, 0x02);  in rt1308_io_init()
241 	regmap_write(rt1308->regmap, 0xc061, 0x75);  in rt1308_io_init()
242 	regmap_write(rt1308->regmap, 0xc062, 0x05);  in rt1308_io_init()
243 	regmap_write(rt1308->regmap, 0xc171, 0x07);  in rt1308_io_init()
244 	regmap_write(rt1308->regmap, 0xc173, 0x0d);  in rt1308_io_init()
245 	regmap_write(rt1308->regmap, 0xc311, 0x7f);  in rt1308_io_init()
246 	regmap_write(rt1308->regmap, 0xc900, 0x90);  in rt1308_io_init()
247 	regmap_write(rt1308->regmap, 0xc1a0, 0x84);  in rt1308_io_init()
248 	regmap_write(rt1308->regmap, 0xc1a1, 0x01);  in rt1308_io_init()
249 	regmap_write(rt1308->regmap, 0xc360, 0x78);  in rt1308_io_init()
250 	regmap_write(rt1308->regmap, 0xc361, 0x87);  in rt1308_io_init()
251 	regmap_write(rt1308->regmap, 0xc0a1, 0x71);  in rt1308_io_init()
252 	regmap_write(rt1308->regmap, 0xc210, 0x00);  in rt1308_io_init()
253 	regmap_write(rt1308->regmap, 0xc070, 0x00);  in rt1308_io_init()
254 	regmap_write(rt1308->regmap, 0xc100, 0xd7);  in rt1308_io_init()
255 	regmap_write(rt1308->regmap, 0xc101, 0xd7);  in rt1308_io_init()
256 	regmap_write(rt1308->regmap, 0xc300, 0x09);  in rt1308_io_init()
291 		return 0;  in rt1308_update_status()
306 	if (ret < 0)  in rt1308_bus_config()
318 	return 0;  in rt1308_interrupt_callback()
332 			0x3,	0x3);  in rt1308_classd_event()
338 			0x3, 0);  in rt1308_classd_event()
346 	return 0;  in rt1308_classd_event()
357 	RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
378 	SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
382 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	7, 0, NULL, 0),
384 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	6, 0, NULL, 0),
386 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	5, 0, NULL, 0),
388 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	4, 0, NULL, 0),
390 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	2, 0, NULL, 0),
392 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	1, 0, NULL, 0),
394 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	0, 0, NULL, 0),
396 		RT1308_SDW_OFFSET | (RT1308_POWER << 4),	3, 0, NULL, 0),
399 		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	5, 0, NULL, 0),
401 		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	4, 0, NULL, 0),
403 		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	2, 0, NULL, 0),
405 		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	1, 0, NULL, 0),
407 		RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),	0, 0, NULL, 0),
410 		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
412 		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
414 		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
416 		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
418 		RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
421 	SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
422 	SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
423 	SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
426 	SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
472 		return 0;  in rt1308_set_sdw_stream()
486 	return 0;  in rt1308_set_sdw_stream()
518 	return 0;  in rt1308_sdw_set_tdm_slot()
590 	return 0;  in rt1308_sdw_pcm_hw_free()
683 	return 0;  in rt1308_sdw_probe()
687 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
697 		return 0;  in rt1308_dev_suspend()
701 	return 0;  in rt1308_dev_suspend()
713 		return 0;  in rt1308_dev_resume()
726 	slave->unattach_request = 0;  in rt1308_dev_resume()
728 	regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff);  in rt1308_dev_resume()
730 	return 0;  in rt1308_dev_resume()