Lines Matching +full:0 +full:xc100
42 #define PCI171X_AD_DATA_REG 0x00 /* R: A/D data */
43 #define PCI171X_SOFTTRG_REG 0x00 /* W: soft trigger for A/D */
44 #define PCI171X_RANGE_REG 0x02 /* W: A/D gain/range register */
47 #define PCI171X_RANGE_GAIN(x) (((x) & 0x7) << 0)
48 #define PCI171X_MUX_REG 0x04 /* W: A/D multiplexor control */
49 #define PCI171X_MUX_CHANH(x) (((x) & 0xff) << 8)
50 #define PCI171X_MUX_CHANL(x) (((x) & 0xff) << 0)
52 #define PCI171X_STATUS_REG 0x06 /* R: status register */
57 #define PCI171X_CTRL_REG 0x06 /* W: control register */
58 #define PCI171X_CTRL_CNT0 BIT(6) /* 1=ext. clk, 0=int. 100kHz clk */
59 #define PCI171X_CTRL_ONEFH BIT(5) /* 1=on FIFO half full, 0=on sample */
64 #define PCI171X_CTRL_SW BIT(0) /* 1=enable software trigger source */
65 #define PCI171X_CLRINT_REG 0x08 /* W: clear interrupts request */
66 #define PCI171X_CLRFIFO_REG 0x09 /* W: clear FIFO */
67 #define PCI171X_DA_REG(x) (0x0a + ((x) * 2)) /* W: D/A register */
68 #define PCI171X_DAREF_REG 0x0e /* W: D/A reference control */
69 #define PCI171X_DAREF(c, r) (((r) & 0x3) << ((c) * 2))
70 #define PCI171X_DAREF_MASK(c) PCI171X_DAREF((c), 0x3)
71 #define PCI171X_DI_REG 0x10 /* R: digital inputs */
72 #define PCI171X_DO_REG 0x10 /* W: digital outputs */
73 #define PCI171X_TIMER_BASE 0x18 /* R/W: 8254 timer */
77 BIP_RANGE(5), /* gain 1 (0x00) */
78 BIP_RANGE(2.5), /* gain 2 (0x01) */
79 BIP_RANGE(1.25), /* gain 4 (0x02) */
80 BIP_RANGE(0.625), /* gain 8 (0x03) */
81 BIP_RANGE(10), /* gain 0.5 (0x04) */
82 UNI_RANGE(10), /* gain 1 (0x00 | UNI) */
83 UNI_RANGE(5), /* gain 2 (0x01 | UNI) */
84 UNI_RANGE(2.5), /* gain 4 (0x02 | UNI) */
85 UNI_RANGE(1.25) /* gain 8 (0x03 | UNI) */
91 BIP_RANGE(5), /* gain 1 (0x00) */
92 BIP_RANGE(0.5), /* gain 10 (0x01) */
93 BIP_RANGE(0.05), /* gain 100 (0x02) */
94 BIP_RANGE(0.005), /* gain 1000 (0x03) */
95 BIP_RANGE(10), /* gain 0.5 (0x04) */
96 BIP_RANGE(1), /* gain 5 (0x05) */
97 BIP_RANGE(0.1), /* gain 50 (0x06) */
98 BIP_RANGE(0.01), /* gain 500 (0x07) */
99 UNI_RANGE(10), /* gain 1 (0x00 | UNI) */
100 UNI_RANGE(1), /* gain 10 (0x01 | UNI) */
101 UNI_RANGE(0.1), /* gain 100 (0x02 | UNI) */
102 UNI_RANGE(0.01) /* gain 1000 (0x03 | UNI) */
108 BIP_RANGE(10), /* gain 1 (0x00) */
109 BIP_RANGE(5), /* gain 2 (0x01) */
110 BIP_RANGE(2.5), /* gain 4 (0x02) */
111 BIP_RANGE(1.25), /* gain 8 (0x03) */
112 BIP_RANGE(0.625) /* gain 16 (0x04) */
120 RANGE_ext(0, 1) /* external -Vref (+/-10V max) */
186 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]); in pci1710_ai_check_chanlist()
187 unsigned int last_aref = CR_AREF(cmd->chanlist[0]); in pci1710_ai_check_chanlist()
195 return 0; in pci1710_ai_check_chanlist()
199 chansegment[0] = cmd->chanlist[0]; in pci1710_ai_check_chanlist()
205 if (cmd->chanlist[0] == cmd->chanlist[i]) in pci1710_ai_check_chanlist()
229 for (i = 0; i < cmd->chanlist_len; i++) { in pci1710_ai_check_chanlist()
244 return 0; in pci1710_ai_check_chanlist()
254 unsigned int first_chan = CR_CHAN(chanlist[0]); in pci1710_ai_setup_chanlist()
258 for (i = 0; i < seglen; i++) { /* store range list to card */ in pci1710_ai_setup_chanlist()
262 unsigned int rangeval = 0; in pci1710_ai_setup_chanlist()
295 if ((status & PCI171X_STATUS_FE) == 0) in pci1710_ai_eoc()
296 return 0; in pci1710_ai_eoc()
326 return 0; in pci1710_ai_read_sample()
335 int ret = 0; in pci1710_ai_insn_read()
342 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_ai_insn_read()
343 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_insn_read()
347 for (i = 0; i < insn->n; i++) { in pci1710_ai_insn_read()
351 outw(0, dev->iobase + PCI171X_SOFTTRG_REG); in pci1710_ai_insn_read()
353 ret = comedi_timeout(dev, s, insn, pci1710_ai_eoc, 0); in pci1710_ai_insn_read()
357 ret = pci1710_ai_read_sample(dev, s, 0, &val); in pci1710_ai_insn_read()
368 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_ai_insn_read()
369 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_insn_read()
380 devpriv->ctrl &= PCI171X_CTRL_CNT0; /* preserve counter 0 clk src */ in pci1710_ai_cancel()
387 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_ai_cancel()
388 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_cancel()
390 return 0; in pci1710_ai_cancel()
414 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_handle_every_sample()
432 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_handle_every_sample()
457 for (i = 0; i < devpriv->max_samples; i++) { in pci1710_handle_fifo()
477 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_handle_fifo()
498 devpriv->ai_et = 0; in pci1710_irq_handler()
503 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_irq_handler()
504 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_irq_handler()
530 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_ai_cmd()
531 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_cmd()
534 if ((cmd->flags & CMDF_WAKE_EOS) == 0) in pci1710_ai_cmd()
549 devpriv->ai_et = 0; in pci1710_ai_cmd()
560 return 0; in pci1710_ai_cmd()
567 int err = 0; in pci1710_ai_cmdtest()
594 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); in pci1710_ai_cmdtest()
595 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0); in pci1710_ai_cmdtest()
600 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); in pci1710_ai_cmdtest()
608 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); in pci1710_ai_cmdtest()
632 return 0; in pci1710_ai_cmdtest()
650 for (i = 0; i < insn->n; i++) { in pci1710_ao_insn_write()
690 switch (data[0]) { in pci1710_counter_insn_config()
693 case 0: /* internal */ in pci1710_counter_insn_config()
707 data[2] = 0; in pci1710_counter_insn_config()
709 data[1] = 0; in pci1710_counter_insn_config()
725 * Disable A/D triggers and interrupt sources, set counter 0 in pci1710_reset()
728 outw(0, dev->iobase + PCI171X_CTRL_REG); in pci1710_reset()
731 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_reset()
732 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_reset()
735 /* set DACs to 0..5V and outputs to 0V */ in pci1710_reset()
736 outb(0, dev->iobase + PCI171X_DAREF_REG); in pci1710_reset()
737 outw(0, dev->iobase + PCI171X_DA_REG(0)); in pci1710_reset()
738 outw(0, dev->iobase + PCI171X_DA_REG(1)); in pci1710_reset()
741 /* set digital outputs to 0 */ in pci1710_reset()
742 outw(0, dev->iobase + PCI171X_DO_REG); in pci1710_reset()
772 I8254_OSC_BASE_10MHZ, I8254_IO16, 0); in pci1710_auto_attach()
796 if (ret == 0) in pci1710_auto_attach()
800 subdev = 0; in pci1710_auto_attach()
809 s->maxdata = 0x0fff; in pci1710_auto_attach()
822 for (i = 0; i < s->range_table->length; i++) { in pci1710_auto_attach()
835 s->maxdata = 0x0fff; in pci1710_auto_attach()
877 return 0; in pci1710_auto_attach()
896 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
900 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
901 PCI_VENDOR_ID_ADVANTECH, 0x0000),
904 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
905 PCI_VENDOR_ID_ADVANTECH, 0xb100),
908 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
909 PCI_VENDOR_ID_ADVANTECH, 0xb200),
912 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
913 PCI_VENDOR_ID_ADVANTECH, 0xc100),
916 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
917 PCI_VENDOR_ID_ADVANTECH, 0xc200),
920 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710, 0x1000, 0xd100),
923 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
924 PCI_VENDOR_ID_ADVANTECH, 0x0002),
927 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
928 PCI_VENDOR_ID_ADVANTECH, 0xb102),
931 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
932 PCI_VENDOR_ID_ADVANTECH, 0xb202),
935 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
936 PCI_VENDOR_ID_ADVANTECH, 0xc102),
939 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710,
940 PCI_VENDOR_ID_ADVANTECH, 0xc202),
943 PCI_DEVICE_SUB(PCI_VENDOR_ID_ADVANTECH, 0x1710, 0x1000, 0xd102),
946 { PCI_VDEVICE(ADVANTECH, 0x1711), BOARD_PCI1711 },
947 { PCI_VDEVICE(ADVANTECH, 0x1713), BOARD_PCI1713 },
948 { PCI_VDEVICE(ADVANTECH, 0x1731), BOARD_PCI1731 },
949 { 0 }