Searched refs:temp_ctl (Results 1 – 2 of 2) sorted by relevance
476 unsigned int temp_ctl = 0; in tsi148_slave_set() local539 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()541 temp_ctl &= ~TSI148_LCSR_ITAT_EN; in tsi148_slave_set()542 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + in tsi148_slave_set()560 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; in tsi148_slave_set()563 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160; in tsi148_slave_set()566 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267; in tsi148_slave_set()569 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320; in tsi148_slave_set()574 temp_ctl &= ~(0x1F << 7); in tsi148_slave_set()576 temp_ctl |= TSI148_LCSR_ITAT_BLT; in tsi148_slave_set()[all …]
338 unsigned int temp_ctl = 0; in ca91cx42_slave_set() local404 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()405 temp_ctl &= ~CA91CX42_VSI_CTL_EN; in ca91cx42_slave_set()406 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()414 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M; in ca91cx42_slave_set()415 temp_ctl |= addr; in ca91cx42_slave_set()418 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M); in ca91cx42_slave_set()420 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR; in ca91cx42_slave_set()422 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV; in ca91cx42_slave_set()424 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM; in ca91cx42_slave_set()[all …]
