476 	unsigned int temp_ctl = 0;  in tsi148_slave_set()  local
539 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
541 	temp_ctl &= ~TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
542 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
560 	temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;  in tsi148_slave_set()
563 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;  in tsi148_slave_set()
566 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;  in tsi148_slave_set()
569 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;  in tsi148_slave_set()
574 	temp_ctl &= ~(0x1F << 7);  in tsi148_slave_set()
576 		temp_ctl |= TSI148_LCSR_ITAT_BLT;  in tsi148_slave_set()
578 		temp_ctl |= TSI148_LCSR_ITAT_MBLT;  in tsi148_slave_set()
580 		temp_ctl |= TSI148_LCSR_ITAT_2eVME;  in tsi148_slave_set()
582 		temp_ctl |= TSI148_LCSR_ITAT_2eSST;  in tsi148_slave_set()
584 		temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;  in tsi148_slave_set()
587 	temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;  in tsi148_slave_set()
588 	temp_ctl |= addr;  in tsi148_slave_set()
590 	temp_ctl &= ~0xF;  in tsi148_slave_set()
592 		temp_ctl |= TSI148_LCSR_ITAT_SUPR ;  in tsi148_slave_set()
594 		temp_ctl |= TSI148_LCSR_ITAT_NPRIV;  in tsi148_slave_set()
596 		temp_ctl |= TSI148_LCSR_ITAT_PGM;  in tsi148_slave_set()
598 		temp_ctl |= TSI148_LCSR_ITAT_DATA;  in tsi148_slave_set()
601 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
605 		temp_ctl |= TSI148_LCSR_ITAT_EN;  in tsi148_slave_set()
607 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
813 	unsigned int temp_ctl = 0;  in tsi148_master_set()  local
903 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
905 	temp_ctl &= ~TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
906 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
910 	temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;  in tsi148_master_set()
913 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;  in tsi148_master_set()
916 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;  in tsi148_master_set()
919 		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;  in tsi148_master_set()
925 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
926 		temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;  in tsi148_master_set()
929 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
930 		temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;  in tsi148_master_set()
933 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
934 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;  in tsi148_master_set()
937 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
938 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;  in tsi148_master_set()
943 		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;  in tsi148_master_set()
944 		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;  in tsi148_master_set()
948 	temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;  in tsi148_master_set()
951 		temp_ctl |= TSI148_LCSR_OTAT_DBW_16;  in tsi148_master_set()
954 		temp_ctl |= TSI148_LCSR_OTAT_DBW_32;  in tsi148_master_set()
964 	temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;  in tsi148_master_set()
967 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;  in tsi148_master_set()
970 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;  in tsi148_master_set()
973 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;  in tsi148_master_set()
976 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;  in tsi148_master_set()
979 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;  in tsi148_master_set()
982 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;  in tsi148_master_set()
985 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;  in tsi148_master_set()
988 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;  in tsi148_master_set()
991 		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;  in tsi148_master_set()
1001 	temp_ctl &= ~(3<<4);  in tsi148_master_set()
1003 		temp_ctl |= TSI148_LCSR_OTAT_SUP;  in tsi148_master_set()
1005 		temp_ctl |= TSI148_LCSR_OTAT_PGM;  in tsi148_master_set()
1022 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1026 		temp_ctl |= TSI148_LCSR_OTAT_EN;  in tsi148_master_set()
1028 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()