338 	unsigned int temp_ctl = 0;  in ca91cx42_slave_set()  local
404 	temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
405 	temp_ctl &= ~CA91CX42_VSI_CTL_EN;  in ca91cx42_slave_set()
406 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
414 	temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;  in ca91cx42_slave_set()
415 	temp_ctl |= addr;  in ca91cx42_slave_set()
418 	temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);  in ca91cx42_slave_set()
420 		temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;  in ca91cx42_slave_set()
422 		temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;  in ca91cx42_slave_set()
424 		temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;  in ca91cx42_slave_set()
426 		temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;  in ca91cx42_slave_set()
429 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
432 		temp_ctl |= CA91CX42_VSI_CTL_EN;  in ca91cx42_slave_set()
434 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
595 	unsigned int temp_ctl = 0;  in ca91cx42_master_set()  local
650 	temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
651 	temp_ctl &= ~CA91CX42_LSI_CTL_EN;  in ca91cx42_master_set()
652 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
655 	temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;  in ca91cx42_master_set()
657 		temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;  in ca91cx42_master_set()
659 		temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;  in ca91cx42_master_set()
662 	temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;  in ca91cx42_master_set()
665 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;  in ca91cx42_master_set()
668 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;  in ca91cx42_master_set()
671 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;  in ca91cx42_master_set()
674 		temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;  in ca91cx42_master_set()
685 	temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;  in ca91cx42_master_set()
688 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;  in ca91cx42_master_set()
691 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;  in ca91cx42_master_set()
694 		temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;  in ca91cx42_master_set()
697 		temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;  in ca91cx42_master_set()
700 		temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;  in ca91cx42_master_set()
703 		temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;  in ca91cx42_master_set()
716 	temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);  in ca91cx42_master_set()
718 		temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;  in ca91cx42_master_set()
720 		temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;  in ca91cx42_master_set()
728 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
731 		temp_ctl |= CA91CX42_LSI_CTL_EN;  in ca91cx42_master_set()
733 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()