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Searched refs:phy_write (Results 1 – 25 of 87) sorted by relevance

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/Linux-v5.4/drivers/net/phy/
Dvitesse.c94 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
103 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
129 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
131 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
145 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
147 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
148 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
151 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
154 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
[all …]
Dnational.c56 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
62 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
63 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
71 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
74 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
87 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
96 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
99 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
100 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
101 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
[all …]
Dbcm7xxx.c73 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
101 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
225 ret = phy_write(dev, location, v); in phy_set_clr_bits()
243 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
248 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
258 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
314 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
318 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
324 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
328 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
[all …]
Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
Dbcm-phy-lib.c21 rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_write_exp()
25 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); in bcm_phy_write_exp()
33 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_read_exp()
40 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0); in bcm_phy_read_exp()
51 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK | in bcm54xx_auxctl_read()
59 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
69 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
76 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
93 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
100 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
[all …]
Dmeson-gxl.c55 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
58 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
61 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
64 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
69 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
81 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
105 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
109 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
222 return phy_write(phydev, INTSRC_MASK, val); in meson_gxl_config_intr()
Ddavicom.c75 temp = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
85 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
104 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
121 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
126 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
132 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
Ddp83tc811.c210 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
225 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
237 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
240 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
244 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
248 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
261 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
266 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
282 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
285 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
Dat803x.c91 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_read()
112 return phy_write(phydev, AT803X_DEBUG_DATA, val); in at803x_debug_reg_mask()
155 phy_write(phydev, MII_BMCR, context->bmcr); in at803x_context_restore()
156 phy_write(phydev, MII_ADVERTISE, context->advertise); in at803x_context_restore()
157 phy_write(phydev, MII_CTRL1000, context->control1000); in at803x_context_restore()
158 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); in at803x_context_restore()
159 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); in at803x_context_restore()
160 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); in at803x_context_restore()
191 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); in at803x_set_wol()
198 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); in at803x_set_wol()
[all …]
Drealtek.c110 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
113 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
123 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
126 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
155 phy_write(phydev, 0x17, 0x2138); in rtl8211_config_aneg()
156 phy_write(phydev, 0x0e, 0x0260); in rtl8211_config_aneg()
158 phy_write(phydev, 0x17, 0x2108); in rtl8211_config_aneg()
159 phy_write(phydev, 0x0e, 0x0000); in rtl8211_config_aneg()
243 phy_write(phydev, MII_MMD_DATA, BIT(9)); in rtl8211b_suspend()
250 phy_write(phydev, MII_MMD_DATA, 0); in rtl8211b_resume()
[all …]
Dcicada.c67 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT, in cis820x_config_init()
73 err = phy_write(phydev, MII_CIS8201_EXT_CON1, in cis820x_config_init()
91 err = phy_write(phydev, MII_CIS8201_IMASK, in cis820x_config_intr()
94 err = phy_write(phydev, MII_CIS8201_IMASK, 0); in cis820x_config_intr()
Dlxt.c79 return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); in lxt970_config_intr()
81 return phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
86 return phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
103 return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); in lxt971_config_intr()
105 return phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
234 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
42 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
244 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); in lan88xx_probe()
296 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan88xx_set_mdix()
300 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf); in lan88xx_set_mdix()
301 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan88xx_set_mdix()
Dqsemi.c71 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); in qs6612_config_init()
100 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
103 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
Dbcm63xx.c33 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_intr()
50 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
59 return phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
Dste10Xp.c40 err = phy_write(phydev, MII_BMCR, value); in ste10Xp_config_init()
57 err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK); in ste10Xp_config_intr()
65 err = phy_write(phydev, MII_XIE, 0); in ste10Xp_config_intr()
Ddp83822.c209 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); in dp83822_config_intr()
226 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); in dp83822_config_intr()
237 err = phy_write(phydev, MII_DP83822_MISR1, 0); in dp83822_config_intr()
241 err = phy_write(phydev, MII_DP83822_MISR1, 0); in dp83822_config_intr()
252 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); in dp83822_config_intr()
269 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_HW_RESET); in dp83822_phy_reset()
/Linux-v5.4/arch/arm/mach-imx/
Dmach-imx6q.c41 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
43 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
46 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
48 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
49 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
58 phy_write(dev, 0x0d, device); in mmd_write_reg()
59 phy_write(dev, 0x0e, reg); in mmd_write_reg()
60 phy_write(dev, 0x0d, (1 << 14) | device); in mmd_write_reg()
61 phy_write(dev, 0x0e, val); in mmd_write_reg()
110 phy_write(dev, 0xd, 0x7); in ar8031_phy_fixup()
[all …]
Dmach-imx7d.c22 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
23 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
26 phy_write(dev, 0xd, 0x3); in ar8031_phy_fixup()
27 phy_write(dev, 0xe, 0x805d); in ar8031_phy_fixup()
28 phy_write(dev, 0xd, 0x4003); in ar8031_phy_fixup()
31 phy_write(dev, 0xe, val); in ar8031_phy_fixup()
39 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
40 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
41 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
42 phy_write(dev, 0x1f, 0x71b7); in bcm54220_phy_fixup()
Dmach-imx6ul.c34 phy_write(dev, 0x1f, 0x8110); in ksz8081_phy_fixup()
35 phy_write(dev, 0x16, 0x201); in ksz8081_phy_fixup()
37 phy_write(dev, 0x1f, 0x8190); in ksz8081_phy_fixup()
38 phy_write(dev, 0x16, 0x202); in ksz8081_phy_fixup()
Dmach-imx6sx.c23 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
24 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
27 phy_write(dev, 0x1d, 0x5); in ar8031_phy_fixup()
30 phy_write(dev, 0x1e, val); in ar8031_phy_fixup()
/Linux-v5.4/drivers/net/ethernet/ibm/emac/
Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/Linux-v5.4/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c110 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
292 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
293 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
294 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
295 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
296 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
297 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
298 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
314 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
315 phy_write(phy, CN(priv->cfg.cn), DPHY_CN); in mixel_dphy_set_pll_params()
[all …]
/Linux-v5.4/drivers/staging/mt7621-pci-phy/
Dpci-mt7621-phy.c118 static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32 reg) in phy_write() function
133 phy_write(phy, reg, offset); in mt7621_bypass_pipe_rst()
151 phy_write(phy, val, RG_PE1_FRC_H_XTAL_REG); in mt7621_set_phy_for_ssc()
159 phy_write(phy, val, offset); in mt7621_set_phy_for_ssc()
167 phy_write(phy, val, RG_PE1_H_PLL_REG); in mt7621_set_phy_for_ssc()
171 phy_write(phy, val, RG_PE1_H_PLL_REG); in mt7621_set_phy_for_ssc()
179 phy_write(phy, val, RG_PE1_H_PLL_FBKSEL_REG); in mt7621_set_phy_for_ssc()
185 phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG); in mt7621_set_phy_for_ssc()
191 phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG); in mt7621_set_phy_for_ssc()
199 phy_write(phy, val, RG_PE1_H_LCDDS_SSC_DELTA_REG); in mt7621_set_phy_for_ssc()
[all …]
/Linux-v5.4/arch/powerpc/platforms/85xx/
Dmpc85xx_mds.c77 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
82 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in mpc8568_fixup_125_clock()
92 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
103 err = phy_write(phydev,29, 0x0006); in mpc8568_mds_phy_fixups()
114 err = phy_write(phydev,30, temp); in mpc8568_mds_phy_fixups()
119 err = phy_write(phydev,29, 0x000a); in mpc8568_mds_phy_fixups()
136 err = phy_write(phydev,30,temp); in mpc8568_mds_phy_fixups()
148 err = phy_write(phydev,16,temp); in mpc8568_mds_phy_fixups()

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