94 	err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);  in vsc824x_add_skew()
103 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc824x_config_init()
129 	phy_write(phydev, 0x1f, 0x2a30);  in vsc73xx_config_init()
131 	phy_write(phydev, 0x1f, 0x0000);  in vsc73xx_config_init()
145 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
147 	phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
148 	phy_write(phydev, 0x10, 0xb68a);  in vsc738x_config_init()
151 	phy_write(phydev, 0x10, 0x968a);  in vsc738x_config_init()
152 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
154 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
162 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
164 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
165 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
166 		phy_write(phydev, 0x11, 0x0689);  in vsc738x_config_init()
167 		phy_write(phydev, 0x10, 0x8f92);  in vsc738x_config_init()
168 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
169 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
170 		phy_write(phydev, 0x11, 0x0e35);  in vsc738x_config_init()
171 		phy_write(phydev, 0x10, 0x9786);  in vsc738x_config_init()
172 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
174 		phy_write(phydev, 0x17, 0xff80);  in vsc738x_config_init()
175 		phy_write(phydev, 0x17, 0x0000);  in vsc738x_config_init()
178 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
179 	phy_write(phydev, 0x12, 0x0048);  in vsc738x_config_init()
182 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
183 		phy_write(phydev, 0x14, 0x6600);  in vsc738x_config_init()
184 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
185 		phy_write(phydev, 0x18, 0xa24e);  in vsc738x_config_init()
187 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
193 		phy_write(phydev, 0x1f, 0x0001);  in vsc738x_config_init()
195 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
210 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
212 	phy_write(phydev, 0x1f, 0x52b5);  in vsc739x_config_init()
213 	phy_write(phydev, 0x10, 0xb68a);  in vsc739x_config_init()
216 	phy_write(phydev, 0x10, 0x968a);  in vsc739x_config_init()
217 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
219 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
221 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
222 	phy_write(phydev, 0x12, 0x0048);  in vsc739x_config_init()
223 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
226 	phy_write(phydev, 0x1f, 0x0001);  in vsc739x_config_init()
228 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
257 	return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);  in vsc8601_add_skew()
292 		err = phy_write(phydev, MII_VSC8244_IMASK,  in vsc82xx_config_intr()
308 		err = phy_write(phydev, MII_VSC8244_IMASK, 0);  in vsc82xx_config_intr()
318 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc8221_config_init()
341 	ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);  in vsc82x4_config_autocross_enable()
343 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);  in vsc82x4_config_autocross_enable()
345 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);  in vsc82x4_config_autocross_enable()
347 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);  in vsc82x4_config_autocross_enable()
350 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
352 		phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()