Home
last modified time | relevance | path

Searched refs:iommu (Results 1 – 25 of 249) sorted by relevance

12345678910

/Linux-v5.4/drivers/iommu/
Damd_iommu_init.c259 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
261 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
265 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
267 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
270 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
274 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
276 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
300 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
304 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
305 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
[all …]
Drockchip-iommu.c107 struct iommu_device iommu; member
115 struct rk_iommu *iommu; member
285 static void rk_iommu_command(struct rk_iommu *iommu, u32 command) in rk_iommu_command() argument
289 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_command()
290 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
297 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, in rk_iommu_zap_lines() argument
306 for (i = 0; i < iommu->num_mmu; i++) { in rk_iommu_zap_lines()
310 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
314 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) in rk_iommu_is_stall_active() argument
319 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_is_stall_active()
[all …]
Dmsm_iommu.c55 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
59 ret = clk_enable(iommu->pclk); in __enable_clocks()
63 if (iommu->clk) { in __enable_clocks()
64 ret = clk_enable(iommu->clk); in __enable_clocks()
66 clk_disable(iommu->pclk); in __enable_clocks()
72 static void __disable_clocks(struct msm_iommu_dev *iommu) in __disable_clocks() argument
74 if (iommu->clk) in __disable_clocks()
75 clk_disable(iommu->clk); in __disable_clocks()
76 clk_disable(iommu->pclk); in __disable_clocks()
121 struct msm_iommu_dev *iommu = NULL; in __flush_iotlb() local
[all …]
Dintel_irq_remapping.c32 struct intel_iommu *iommu; member
39 struct intel_iommu *iommu; member
46 struct intel_iommu *iommu; member
82 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
85 static bool ir_pre_enabled(struct intel_iommu *iommu) in ir_pre_enabled() argument
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); in ir_pre_enabled()
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu) in clear_ir_pre_enabled() argument
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; in clear_ir_pre_enabled()
95 static void init_ir_status(struct intel_iommu *iommu) in init_ir_status() argument
99 gsts = readl(iommu->reg + DMAR_GSTS_REG); in init_ir_status()
[all …]
Ddmar.c64 static void free_iommu(struct intel_iommu *iommu);
431 if (dmaru->iommu) in dmar_free_drhd()
432 free_iommu(dmaru->iommu); in dmar_free_drhd()
470 drhd->iommu->node = node; in dmar_parse_one_rhsa()
899 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
911 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
913 iounmap(iommu->reg); in unmap_iommu()
914 release_mem_region(iommu->reg_phys, iommu->reg_size); in unmap_iommu()
925 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) in map_iommu() argument
929 iommu->reg_phys = phys_addr; in map_iommu()
[all …]
Diommu-sysfs.c54 int iommu_device_sysfs_add(struct iommu_device *iommu, in iommu_device_sysfs_add() argument
62 iommu->dev = kzalloc(sizeof(*iommu->dev), GFP_KERNEL); in iommu_device_sysfs_add()
63 if (!iommu->dev) in iommu_device_sysfs_add()
66 device_initialize(iommu->dev); in iommu_device_sysfs_add()
68 iommu->dev->class = &iommu_class; in iommu_device_sysfs_add()
69 iommu->dev->parent = parent; in iommu_device_sysfs_add()
70 iommu->dev->groups = groups; in iommu_device_sysfs_add()
73 ret = kobject_set_name_vargs(&iommu->dev->kobj, fmt, vargs); in iommu_device_sysfs_add()
78 ret = device_add(iommu->dev); in iommu_device_sysfs_add()
82 dev_set_drvdata(iommu->dev, iommu); in iommu_device_sysfs_add()
[all …]
Dintel-iommu.c344 static void domain_context_clear(struct intel_iommu *iommu,
347 struct intel_iommu *iommu);
412 static bool translation_pre_enabled(struct intel_iommu *iommu) in translation_pre_enabled() argument
414 return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
417 static void clear_translation_pre_enabled(struct intel_iommu *iommu) in clear_translation_pre_enabled() argument
419 iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
422 static void init_translation_status(struct intel_iommu *iommu) in init_translation_status() argument
426 gsts = readl(iommu->reg + DMAR_GSTS_REG); in init_translation_status()
428 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
484 static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did) in get_iommu_domain() argument
[all …]
Dintel-svm.c26 int intel_svm_init(struct intel_iommu *iommu) in intel_svm_init() argument
29 !cap_fl1gp_support(iommu->cap)) in intel_svm_init()
33 !cap_5lp_support(iommu->cap)) in intel_svm_init()
41 int intel_svm_enable_prq(struct intel_iommu *iommu) in intel_svm_enable_prq() argument
49 iommu->name); in intel_svm_enable_prq()
52 iommu->prq = page_address(pages); in intel_svm_enable_prq()
54 irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu); in intel_svm_enable_prq()
57 iommu->name); in intel_svm_enable_prq()
60 free_pages((unsigned long)iommu->prq, PRQ_ORDER); in intel_svm_enable_prq()
61 iommu->prq = NULL; in intel_svm_enable_prq()
[all …]
Dintel-pasid.c96 if (info->iommu->segment == data->segment && in search_pasid_table()
133 info = dev->archdata.iommu; in intel_pasid_alloc_table()
155 pages = alloc_pages_node(info->iommu->node, in intel_pasid_alloc_table()
180 info = dev->archdata.iommu; in intel_pasid_free_table()
206 info = dev->archdata.iommu; in intel_pasid_get_table()
217 info = dev->archdata.iommu; in intel_pasid_get_dev_max_id()
238 info = dev->archdata.iommu; in intel_pasid_get_entry()
245 entries = alloc_pgtable_page(info->iommu->node); in intel_pasid_get_entry()
399 pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, in pasid_cache_invalidation_with_pasid() argument
409 qi_submit_sync(&desc, iommu); in pasid_cache_invalidation_with_pasid()
[all …]
Dintel-iommu-debugfs.c108 struct intel_iommu *iommu; in iommu_regset_show() local
114 for_each_active_iommu(iommu, drhd) { in iommu_regset_show()
122 iommu->name, drhd->reg_base_addr); in iommu_regset_show()
128 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_regset_show()
130 value = dmar_readq(iommu->reg + iommu_regs[i].offset); in iommu_regset_show()
135 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_regset_show()
203 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus) in ctx_tbl_walk() argument
225 context = iommu_context_addr(iommu, bus, devfn, 0); in ctx_tbl_walk()
234 tbl_wlk.rt_entry = &iommu->root_entry[bus]; in ctx_tbl_walk()
238 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { in ctx_tbl_walk()
[all …]
DMakefile2 obj-$(CONFIG_IOMMU_API) += iommu.o
3 obj-$(CONFIG_IOMMU_API) += iommu-traces.o
4 obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
5 obj-$(CONFIG_IOMMU_DEBUGFS) += iommu-debugfs.o
6 obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o
19 obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o intel-pasid.o
21 obj-$(CONFIG_INTEL_IOMMU_DEBUGFS) += intel-iommu-debugfs.o
27 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
28 obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
29 obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
[all …]
/Linux-v5.4/arch/sparc/kernel/
Diommu.c52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
80 #define IOPTE_IS_DUMMY(iommu, iopte) \ argument
81 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
83 static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte) in iopte_make_dummy() argument
88 val |= iommu->dummy_page_pa; in iopte_make_dummy()
93 int iommu_table_init(struct iommu *iommu, int tsbsize, in iommu_table_init() argument
[all …]
Diommu-common.c19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
52 void iommu_tbl_pool_init(struct iommu_map_table *iommu, in iommu_tbl_pool_init() argument
60 struct iommu_pool *p = &(iommu->large_pool); in iommu_tbl_pool_init()
64 iommu->nr_pools = IOMMU_NR_POOLS; in iommu_tbl_pool_init()
66 iommu->nr_pools = npools; in iommu_tbl_pool_init()
[all …]
Dsbus.c62 struct iommu *iommu = dev->archdata.iommu; in sbus_set_sbus64() local
77 cfg_reg = iommu->write_complete_reg; in sbus_set_sbus64()
212 struct iommu *iommu = op->dev.archdata.iommu; in sbus_build_irq() local
213 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq()
274 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ue_handler() local
275 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler()
348 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ce_handler() local
349 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler()
427 struct iommu *iommu = op->dev.archdata.iommu; in sysio_sbus_error_handler() local
432 reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_sbus_error_handler()
[all …]
Dpci_sun4v.c76 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
78 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
100 if (!iommu_use_atu(pbm->iommu, mask)) { in iommu_batch_flush()
117 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
186 struct iommu *iommu; in dma_4v_alloc_coherent() local
211 iommu = dev->archdata.iommu; in dma_4v_alloc_coherent()
213 if (!iommu_use_atu(iommu, mask)) in dma_4v_alloc_coherent()
214 tbl = &iommu->tbl; in dma_4v_alloc_coherent()
216 tbl = &iommu->atu->tbl; in dma_4v_alloc_coherent()
325 struct iommu *iommu; in dma_4v_free_coherent() local
[all …]
/Linux-v5.4/drivers/gpu/drm/msm/
Dmsm_iommu.c19 struct msm_iommu *iommu = arg; in msm_fault_handler() local
20 if (iommu->base.handler) in msm_fault_handler()
21 return iommu->base.handler(iommu->base.arg, iova, flags); in msm_fault_handler()
29 struct msm_iommu *iommu = to_msm_iommu(mmu); in msm_iommu_attach() local
31 return iommu_attach_device(iommu->domain, mmu->dev); in msm_iommu_attach()
37 struct msm_iommu *iommu = to_msm_iommu(mmu); in msm_iommu_detach() local
39 iommu_detach_device(iommu->domain, mmu->dev); in msm_iommu_detach()
45 struct msm_iommu *iommu = to_msm_iommu(mmu); in msm_iommu_map() local
48 ret = iommu_map_sg(iommu->domain, iova, sgt->sgl, sgt->nents, prot); in msm_iommu_map()
56 struct msm_iommu *iommu = to_msm_iommu(mmu); in msm_iommu_unmap() local
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt20 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
43 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
44 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
45 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
46 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
47 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
48 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
49 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
50 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
88 iommus = <&iommu M4U_PORT_VENC_RCPU>,
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/pci/
Dpci-iommu.txt26 Documentation/devicetree/bindings/iommu/iommu.txt.
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
42 the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
44 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
45 mapped to an IOMMU specifier per the iommu-map property.
55 iommu: iommu@a {
57 compatible = "vendor,some-iommu";
58 #iommu-cells = <1>;
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
[all …]
/Linux-v5.4/arch/powerpc/platforms/cell/
Diommu.c102 struct cbe_iommu *iommu; member
129 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, in invalidate_tce_cache() argument
136 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; in invalidate_tce_cache()
193 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_build_cell()
216 __pa(window->iommu->pad_page) | in tce_free_cell()
227 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_free_cell()
233 struct cbe_iommu *iommu = data; in ioc_interrupt() local
235 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); in ioc_interrupt()
251 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); in ioc_interrupt()
296 static void cell_iommu_setup_stab(struct cbe_iommu *iommu, in cell_iommu_setup_stab() argument
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
27 - #iommu-cells : Must be 1. Index identifies the context-bank #.
29 - ranges : Base address and size of the iommu context banks.
31 - qcom,iommu-secure-id : secure-id.
37 - "qcom,msm-iommu-v1-ns" : non-secure context bank
38 - "qcom,msm-iommu-v1-sec" : secure context bank
39 - reg : Base address and size of context bank within the iommu
45 be only specified if the iommu requires configuration
47 secure lines. (Ie. if the iommu contains secure
[all …]
/Linux-v5.4/drivers/vfio/
Dvfio_iommu_type1.c124 #define IS_IOMMU_CAP_DOMAIN_IN_CONTAINER(iommu) \ argument
125 (!list_empty(&iommu->domain_list))
134 static struct vfio_dma *vfio_find_dma(struct vfio_iommu *iommu, in vfio_find_dma() argument
137 struct rb_node *node = iommu->dma_list.rb_node; in vfio_find_dma()
153 static void vfio_link_dma(struct vfio_iommu *iommu, struct vfio_dma *new) in vfio_link_dma() argument
155 struct rb_node **link = &iommu->dma_list.rb_node, *parent = NULL; in vfio_link_dma()
169 rb_insert_color(&new->node, &iommu->dma_list); in vfio_link_dma()
172 static void vfio_unlink_dma(struct vfio_iommu *iommu, struct vfio_dma *old) in vfio_unlink_dma() argument
174 rb_erase(&old->node, &iommu->dma_list); in vfio_unlink_dma()
546 struct vfio_iommu *iommu = iommu_data; in vfio_iommu_type1_pin_pages() local
[all …]
/Linux-v5.4/arch/sparc/mm/
Diommu.c59 struct iommu_struct *iommu; in sbus_iommu_init() local
66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
67 if (!iommu) { in sbus_iommu_init()
72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
74 if (!iommu->regs) { in sbus_iommu_init()
79 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
84 sbus_writel(control, &iommu->regs->control); in sbus_iommu_init()
86 iommu_invalidate(iommu->regs); in sbus_iommu_init()
87 iommu->start = IOMMU_START; in sbus_iommu_init()
88 iommu->end = 0xffffffff; in sbus_iommu_init()
[all …]
/Linux-v5.4/Documentation/ABI/testing/
Dsysfs-class-iommu-intel-iommu1 What: /sys/class/iommu/<iommu>/intel-iommu/address
8 intel-iommu with a DMAR DRHD table entry.
10 What: /sys/class/iommu/<iommu>/intel-iommu/cap
18 What: /sys/class/iommu/<iommu>/intel-iommu/ecap
26 What: /sys/class/iommu/<iommu>/intel-iommu/version
/Linux-v5.4/Documentation/devicetree/bindings/virtio/
Dmmio.txt11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
22 have an "iommus" property [1]. Since virtio-iommu itself
24 node cannot have both an "#iommu-cells" and an "iommus"
38 viommu: iommu@3100 {
43 #iommu-cells = <1>
46 [1] Documentation/devicetree/bindings/iommu/iommu.txt
[all …]
Diommu.txt3 When virtio-iommu uses the PCI transport, its programming interface is
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
11 - compatible: Should be "virtio,pci-iommu"
18 - #iommu-cells: Each platform DMA master managed by the IOMMU is assigned
20 For virtio-iommu, #iommu-cells must be 1.
25 virtio-iommu node doesn't have an "iommus" property, and is omitted from
26 the iommu-map property of the root complex.
35 iommu0: iommu@0008 {
36 compatible = "virtio,pci-iommu";
38 #iommu-cells = <1>;
[all …]

12345678910