Home
last modified time | relevance | path

Searched refs:WREG32 (Results 1 – 25 of 141) sorted by relevance

123456

/Linux-v5.4/drivers/misc/habanalabs/goya/
Dgoya_security.c23 WREG32(pb_addr, 0); in goya_pb_set_block()
81 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
104 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
128 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
160 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
180 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
194 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
210 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
228 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
251 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
[all …]
Dgoya_coresight.c243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
257 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in goya_config_stm()
258 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask)); in goya_config_stm()
259 WREG32(base_reg + 0xE70, 0x10); in goya_config_stm()
[all …]
Dgoya.c546 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED); in goya_qman0_set_security()
548 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED); in goya_qman0_set_security()
611 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); in goya_late_init()
620 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, in goya_late_init()
782 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
783 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
785 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
786 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
787 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
789 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman()
[all …]
/Linux-v5.4/drivers/gpu/drm/radeon/
Drv515.c153 WREG32(R_000300_VGA_RENDER_CONTROL, in rv515_vga_render_disable()
218 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); in rv515_mc_rreg()
220 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
231 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); in rv515_mc_wreg()
232 WREG32(MC_IND_DATA, (v)); in rv515_mc_wreg()
233 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
307 WREG32(R_000300_VGA_RENDER_CONTROL, 0); in rv515_mc_stop()
316 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
318 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
319 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
[all …]
Dradeon_bios.c267 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); in ni_read_disabled_bios()
270 WREG32(AVIVO_D1VGA_CONTROL, in ni_read_disabled_bios()
273 WREG32(AVIVO_D2VGA_CONTROL, in ni_read_disabled_bios()
276 WREG32(AVIVO_VGA_RENDER_CONTROL, in ni_read_disabled_bios()
279 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); in ni_read_disabled_bios()
284 WREG32(R600_BUS_CNTL, bus_cntl); in ni_read_disabled_bios()
286 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); in ni_read_disabled_bios()
287 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); in ni_read_disabled_bios()
288 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); in ni_read_disabled_bios()
290 WREG32(R600_ROM_CNTL, rom_cntl); in ni_read_disabled_bios()
[all …]
Drv770.c816 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
819 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip()
822 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
823 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
825 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
826 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
828 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
830 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
843 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
910 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
[all …]
Dvce_v2_0.c45 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
55 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
60 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
65 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
69 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
85 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
91 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
96 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
[all …]
Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v1_0_resume()
124 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v1_0_resume()
128 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v1_0_resume()
129 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v1_0_resume()
134 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v1_0_resume()
135 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v1_0_resume()
139 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v1_0_resume()
143 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v1_0_resume()
145 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
[all …]
Dvce_v1_0.c97 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
99 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
109 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
114 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
118 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
122 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
127 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
131 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
141 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_init_cg()
146 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v1_0_init_cg()
[all …]
Dr600.c126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_rreg()
137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_wreg()
138 WREG32(R600_RCU_DATA, (v)); in r600_rcu_wreg()
148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_rreg()
159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_wreg()
160 WREG32(R600_UVD_CTX_DATA, (v)); in r600_uvd_ctx_wreg()
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
873 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
881 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
889 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
[all …]
Dradeon_i2c.c120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
134 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
139 WREG32(rec->a_clk_reg, temp); in pre_xfer()
142 WREG32(rec->a_data_reg, temp); in pre_xfer()
146 WREG32(rec->en_clk_reg, temp); in pre_xfer()
149 WREG32(rec->en_data_reg, temp); in pre_xfer()
153 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
157 WREG32(rec->mask_data_reg, temp); in pre_xfer()
172 WREG32(rec->mask_clk_reg, temp); in post_xfer()
[all …]
Devergreen_hdmi.c64 WREG32(AZ_HOT_PLUG_CONTROL, tmp); in dce4_audio_enable()
80 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
83 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
87 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
88 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
90 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
91 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
94 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
213 WREG32(AFMT_AVI_INFO0 + offset, in evergreen_set_avi_packet()
[all …]
Dni.c51 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_rreg()
62 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_wreg()
63 WREG32(TN_SMC_IND_DATA_0, (v)); in tn_smc_wreg()
677 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); in ni_mc_load_microcode()
681 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
682 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ni_mc_load_microcode()
686 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ni_mc_load_microcode()
687 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ni_mc_load_microcode()
692 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ni_mc_load_microcode()
695 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
[all …]
Devergreen.c55 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
66 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
67 WREG32(EVERGREEN_CG_IND_DATA, (v)); in eg_cg_wreg()
77 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
88 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
89 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); in eg_pif_phy0_wreg()
99 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
110 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
111 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); in eg_pif_phy1_wreg()
1187 WREG32(CG_SCRATCH1, cg_scratch); in sumo_set_uvd_clocks()
[all …]
Dradeon_legacy_encoders.c94 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); in radeon_legacy_lvds_update()
97 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_update()
102 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_update()
112 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
125 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
129 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
240 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_mode_set()
241 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_mode_set()
242 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); in radeon_legacy_lvds_mode_set()
[all …]
Dcik.c194 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_rreg()
205 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_wreg()
206 WREG32(CIK_DIDT_IND_DATA, (v)); in cik_didt_wreg()
256 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
268 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
270 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1861 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1919 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1920 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1925 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
[all …]
Duvd_v4_2.c52 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_resume()
53 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v4_2_resume()
57 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v4_2_resume()
58 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v4_2_resume()
63 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v4_2_resume()
64 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v4_2_resume()
68 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v4_2_resume()
72 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v4_2_resume()
75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
Dradeon_cursor.c44 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
51 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
58 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
99 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in radeon_show_cursor()
101 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor()
103 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); in radeon_show_cursor()
104 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | in radeon_show_cursor()
110 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, in radeon_show_cursor()
113 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, in radeon_show_cursor()
117 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c84 WREG32(mmBIF_FB_EN, 0); in gmc_v6_0_mc_stop()
88 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v6_0_mc_stop()
102 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v6_0_mc_resume()
106 WREG32(mmBIF_FB_EN, tmp); in gmc_v6_0_mc_resume()
190 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
191 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
195 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
196 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in gmc_v6_0_mc_load_microcode()
200 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in gmc_v6_0_mc_load_microcode()
204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
[all …]
Dgmc_v8_0.c187 WREG32(mmBIF_FB_EN, 0); in gmc_v8_0_mc_stop()
191 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); in gmc_v8_0_mc_stop()
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
208 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
332 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
333 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
337 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
338 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
342 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v8_0_tonga_mc_load_microcode()
345 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
[all …]
Dvce_v3_0.c85 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_rptr()
87 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_rptr()
96 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_rptr()
117 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_wptr()
119 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_wptr()
128 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_wptr()
148 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_set_wptr()
150 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_set_wptr()
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
155 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
[all …]
Dvce_v2_0.c94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
96 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
144 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7); in vce_v2_0_disable_cg()
155 WREG32(mmVCE_CLOCK_GATING_A, tmp); in vce_v2_0_init_cg()
160 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_init_cg()
165 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_init_cg()
175 WREG32(mmVCE_CLOCK_GATING_B, 0xf7); in vce_v2_0_mc_resume()
177 WREG32(mmVCE_LMI_CTRL, 0x00398000); in vce_v2_0_mc_resume()
179 WREG32(mmVCE_LMI_SWAP_CNTL, 0); in vce_v2_0_mc_resume()
180 WREG32(mmVCE_LMI_SWAP_CNTL1, 0); in vce_v2_0_mc_resume()
[all …]
Dgmc_v7_0.c99 WREG32(mmBIF_FB_EN, 0); in gmc_v7_0_mc_stop()
103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v7_0_mc_stop()
116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
120 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v7_0_mc_load_microcode()
220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
[all …]
Duvd_v5_0.c88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr()
259 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v5_0_mc_resume()
261 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v5_0_mc_resume()
266 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
267 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v5_0_mc_resume()
271 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); in uvd_v5_0_mc_resume()
272 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v5_0_mc_resume()
277 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); in uvd_v5_0_mc_resume()
278 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v5_0_mc_resume()
280 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
[all …]
Duvd_v4_2.c90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_ring_set_wptr()
268 WREG32(mmUVD_CGC_GATE, 0); in uvd_v4_2_start()
275 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v4_2_start()
285 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v4_2_start()
286 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); in uvd_v4_2_start()
288 WREG32(mmUVD_LMI_CTRL, 0x203108); in uvd_v4_2_start()
291 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); in uvd_v4_2_start()
293 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v4_2_start()
294 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v4_2_start()
295 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v4_2_start()
[all …]

123456