84 		WREG32(mmBIF_FB_EN, 0);  in gmc_v6_0_mc_stop()
88 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);  in gmc_v6_0_mc_stop()
102 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v6_0_mc_resume()
106 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v6_0_mc_resume()
190 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v6_0_mc_load_microcode()
191 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v6_0_mc_load_microcode()
195 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));  in gmc_v6_0_mc_load_microcode()
196 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));  in gmc_v6_0_mc_load_microcode()
200 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));  in gmc_v6_0_mc_load_microcode()
204 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v6_0_mc_load_microcode()
205 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v6_0_mc_load_microcode()
206 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v6_0_mc_load_microcode()
241 		WREG32((0xb05 + j), 0x00000000);  in gmc_v6_0_mc_program()
242 		WREG32((0xb06 + j), 0x00000000);  in gmc_v6_0_mc_program()
243 		WREG32((0xb07 + j), 0x00000000);  in gmc_v6_0_mc_program()
244 		WREG32((0xb08 + j), 0x00000000);  in gmc_v6_0_mc_program()
245 		WREG32((0xb09 + j), 0x00000000);  in gmc_v6_0_mc_program()
247 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v6_0_mc_program()
259 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v6_0_mc_program()
264 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v6_0_mc_program()
267 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v6_0_mc_program()
269 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v6_0_mc_program()
271 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v6_0_mc_program()
273 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v6_0_mc_program()
274 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v6_0_mc_program()
275 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v6_0_mc_program()
368 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v6_0_flush_gpu_tlb()
428 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_set_fault_enable_default()
459 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v6_0_set_prt()
466 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);  in gmc_v6_0_set_prt()
467 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);  in gmc_v6_0_set_prt()
468 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);  in gmc_v6_0_set_prt()
469 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);  in gmc_v6_0_set_prt()
470 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
471 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
472 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
473 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);  in gmc_v6_0_set_prt()
475 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
476 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
477 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
478 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);  in gmc_v6_0_set_prt()
479 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
480 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
481 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
482 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);  in gmc_v6_0_set_prt()
503 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,  in gmc_v6_0_gart_enable()
511 	WREG32(mmVM_L2_CNTL,  in gmc_v6_0_gart_enable()
518 	WREG32(mmVM_L2_CNTL2,  in gmc_v6_0_gart_enable()
523 	WREG32(mmVM_L2_CNTL3,  in gmc_v6_0_gart_enable()
528 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v6_0_gart_enable()
529 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v6_0_gart_enable()
530 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);  in gmc_v6_0_gart_enable()
531 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v6_0_gart_enable()
533 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v6_0_gart_enable()
534 	WREG32(mmVM_CONTEXT0_CNTL,  in gmc_v6_0_gart_enable()
539 	WREG32(0x575, 0);  in gmc_v6_0_gart_enable()
540 	WREG32(0x576, 0);  in gmc_v6_0_gart_enable()
541 	WREG32(0x577, 0);  in gmc_v6_0_gart_enable()
545 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v6_0_gart_enable()
546 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v6_0_gart_enable()
553 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v6_0_gart_enable()
556 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v6_0_gart_enable()
561 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v6_0_gart_enable()
563 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v6_0_gart_enable()
564 	WREG32(mmVM_CONTEXT1_CNTL,  in gmc_v6_0_gart_enable()
612 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v6_0_gart_disable()
613 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v6_0_gart_disable()
615 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,  in gmc_v6_0_gart_disable()
619 	WREG32(mmVM_L2_CNTL,  in gmc_v6_0_gart_disable()
624 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v6_0_gart_disable()
625 	WREG32(mmVM_L2_CNTL3,  in gmc_v6_0_gart_disable()
1038 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v6_0_soft_reset()
1044 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v6_0_soft_reset()
1073 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1076 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1081 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()
1084 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v6_0_vm_fault_interrupt_state()