99 		WREG32(mmBIF_FB_EN, 0);  in gmc_v7_0_mc_stop()
103 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);  in gmc_v7_0_mc_stop()
116 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v7_0_mc_resume()
120 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v7_0_mc_resume()
207 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v7_0_mc_load_microcode()
208 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v7_0_mc_load_microcode()
212 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v7_0_mc_load_microcode()
213 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v7_0_mc_load_microcode()
217 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v7_0_mc_load_microcode()
220 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v7_0_mc_load_microcode()
221 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v7_0_mc_load_microcode()
222 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v7_0_mc_load_microcode()
267 		WREG32((0xb05 + j), 0x00000000);  in gmc_v7_0_mc_program()
268 		WREG32((0xb06 + j), 0x00000000);  in gmc_v7_0_mc_program()
269 		WREG32((0xb07 + j), 0x00000000);  in gmc_v7_0_mc_program()
270 		WREG32((0xb08 + j), 0x00000000);  in gmc_v7_0_mc_program()
271 		WREG32((0xb09 + j), 0x00000000);  in gmc_v7_0_mc_program()
273 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v7_0_mc_program()
282 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v7_0_mc_program()
287 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v7_0_mc_program()
290 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v7_0_mc_program()
292 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v7_0_mc_program()
294 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v7_0_mc_program()
296 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v7_0_mc_program()
297 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v7_0_mc_program()
298 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v7_0_mc_program()
303 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);  in gmc_v7_0_mc_program()
307 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v7_0_mc_program()
310 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v7_0_mc_program()
440 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v7_0_flush_gpu_tlb()
511 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_set_fault_enable_default()
544 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v7_0_set_prt()
551 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);  in gmc_v7_0_set_prt()
552 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);  in gmc_v7_0_set_prt()
553 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);  in gmc_v7_0_set_prt()
554 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);  in gmc_v7_0_set_prt()
555 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);  in gmc_v7_0_set_prt()
556 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);  in gmc_v7_0_set_prt()
557 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);  in gmc_v7_0_set_prt()
558 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);  in gmc_v7_0_set_prt()
560 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);  in gmc_v7_0_set_prt()
561 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);  in gmc_v7_0_set_prt()
562 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);  in gmc_v7_0_set_prt()
563 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);  in gmc_v7_0_set_prt()
564 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);  in gmc_v7_0_set_prt()
565 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);  in gmc_v7_0_set_prt()
566 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);  in gmc_v7_0_set_prt()
567 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);  in gmc_v7_0_set_prt()
605 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_enable()
615 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_enable()
618 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v7_0_gart_enable()
625 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v7_0_gart_enable()
627 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v7_0_gart_enable()
628 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v7_0_gart_enable()
629 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);  in gmc_v7_0_gart_enable()
630 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v7_0_gart_enable()
632 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v7_0_gart_enable()
637 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_gart_enable()
639 	WREG32(0x575, 0);  in gmc_v7_0_gart_enable()
640 	WREG32(0x576, 0);  in gmc_v7_0_gart_enable()
641 	WREG32(0x577, 0);  in gmc_v7_0_gart_enable()
648 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v7_0_gart_enable()
649 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v7_0_gart_enable()
652 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v7_0_gart_enable()
655 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v7_0_gart_enable()
660 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v7_0_gart_enable()
662 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v7_0_gart_enable()
668 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_gart_enable()
677 		WREG32(mmCHUB_CONTROL, tmp);  in gmc_v7_0_gart_enable()
717 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v7_0_gart_disable()
718 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v7_0_gart_disable()
724 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_disable()
728 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_disable()
729 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v7_0_gart_disable()
812 			WREG32(mc_cg_registers[i], data);  in gmc_v7_0_enable_mc_ls()
829 			WREG32(mc_cg_registers[i], data);  in gmc_v7_0_enable_mc_mgcg()
869 		WREG32(mmHDP_HOST_PATH_CNTL, data);  in gmc_v7_0_enable_hdp_mgcg()
885 		WREG32(mmHDP_MEM_POWER_LS, data);  in gmc_v7_0_enable_hdp_ls()
1183 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1189 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1220 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1224 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1230 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1234 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()