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Searched refs:SOC15_REG_OFFSET (Results 1 – 25 of 37) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvce_v4_0.c66 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr()
68 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); in vce_v4_0_ring_get_rptr()
70 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); in vce_v4_0_ring_get_rptr()
88 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
90 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
92 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); in vce_v4_0_ring_get_wptr()
114 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), in vce_v4_0_ring_set_wptr()
117 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), in vce_v4_0_ring_set_wptr()
120 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), in vce_v4_0_ring_set_wptr()
131 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded()
[all …]
Dpsp_v12_0.c105 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sysdrv()
125 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sysdrv()
146 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sos()
165 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v12_0_bootloader_load_sos()
187 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_reroute_ih()
199 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_reroute_ih()
262 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_create()
284 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_ring_create()
310 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_stop()
313 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_ring_stop()
[all …]
Damdgpu_amdkfd_gfx_v9.c141 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
142 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
169 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
172 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping()
178 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping()
183 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
186 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
189 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping()
195 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping()
200 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
[all …]
Damdgpu_amdkfd_gfx_v10.c230 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_program_sh_mem_settings()
231 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_program_sh_mem_settings()
259 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid); in kgd_set_pasid_vmid_mapping()
260 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, in kgd_set_pasid_vmid_mapping()
265 while (!(RREG32(SOC15_REG_OFFSET( in kgd_set_pasid_vmid_mapping()
272 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_set_pasid_vmid_mapping()
279 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_set_pasid_vmid_mapping()
300 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_init_interrupts()
314 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_base_addr()
322 SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_base_addr()
[all …]
Dpsp_v3_1.c145 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sysdrv()
165 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sysdrv()
208 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sos()
227 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v3_1_bootloader_load_sos()
279 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_reroute_ih()
291 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_reroute_ih()
328 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, in psp_v3_1_ring_create()
351 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, in psp_v3_1_ring_create()
376 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v3_1_ring_stop()
388 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_ring_stop()
[all …]
Dpsp_v10_0.c147 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v10_0_ring_create()
168 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v10_0_ring_stop()
259 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); in psp_v10_0_sram_map()
260 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); in psp_v10_0_sram_map()
265 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); in psp_v10_0_sram_map()
266 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); in psp_v10_0_sram_map()
271 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); in psp_v10_0_sram_map()
272 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); in psp_v10_0_sram_map()
277 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v10_0_sram_map()
278 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v10_0_sram_map()
[all …]
Duvd_v7_0.c550 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
555 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
560 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
566 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
570 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
800 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
804 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
807 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
810 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
813 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
[all …]
Dvcn_v1_0.c134 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v1_0_sw_init()
136 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v1_0_sw_init()
138 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v1_0_sw_init()
140 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v1_0_sw_init()
142 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v1_0_sw_init()
160 SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); in vcn_v1_0_sw_init()
801 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start_spg_mode()
850 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
854 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_start_spg_mode()
876 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start_spg_mode()
[all …]
Dmxgpu_ai.c56 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
66 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
138 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
142 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
144 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg()
146 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg()
187 SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_get_pp_clk()
256 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
303 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
[all …]
Dpsp_v11_0.c226 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v11_0_bootloader_load_kdb()
244 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v11_0_bootloader_load_kdb()
268 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v11_0_bootloader_load_sysdrv()
288 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v11_0_bootloader_load_sysdrv()
309 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v11_0_bootloader_load_sos()
328 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v11_0_bootloader_load_sos()
350 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v11_0_reroute_ih()
362 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v11_0_reroute_ih()
425 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_ring_create()
447 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v11_0_ring_create()
[all …]
Dsoc15.c168 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); in soc15_uvd_ctx_rreg()
169 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); in soc15_uvd_ctx_rreg()
182 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); in soc15_uvd_ctx_wreg()
183 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); in soc15_uvd_ctx_wreg()
196 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_rreg()
197 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_rreg()
210 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_wreg()
211 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_wreg()
315 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); in soc15_read_bios_from_rom()
318 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); in soc15_read_bios_from_rom()
[all …]
Dumc_v6_1.c88 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); in umc_v6_1_query_correctable_error_count()
90 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); in umc_v6_1_query_correctable_error_count()
92 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_1_query_correctable_error_count()
134 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_1_querry_uncorrectable_error_count()
171 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_1_query_error_address()
220 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); in umc_v6_1_ras_init_per_channel()
222 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); in umc_v6_1_ras_init_per_channel()
Dnbio_v2_3.c61 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in nbio_v2_3_hdp_flush()
74 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : in nbio_v2_3_sdma_doorbell_range()
75 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); in nbio_v2_3_sdma_doorbell_range()
97 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); in nbio_v2_3_vcn_doorbell_range()
251 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); in nbio_v2_3_get_hdp_flush_req_offset()
256 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); in nbio_v2_3_get_hdp_flush_done_offset()
261 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v2_3_get_pcie_index_offset()
266 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v2_3_get_pcie_data_offset()
Dnbio_v7_4.c101 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); in nbio_v7_4_sdma_doorbell_range()
112 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); in nbio_v7_4_sdma_doorbell_range()
132 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); in nbio_v7_4_vcn_doorbell_range()
134 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); in nbio_v7_4_vcn_doorbell_range()
251 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); in nbio_v7_4_get_hdp_flush_req_offset()
256 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); in nbio_v7_4_get_hdp_flush_done_offset()
261 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v7_4_get_pcie_index_offset()
266 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v7_4_get_pcie_data_offset()
Damdgpu_amdkfd_arcturus.c77 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_base_addr()
79 SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_base_addr()
81 SOC15_REG_OFFSET(SDMA2, 0, in get_sdma_base_addr()
83 SOC15_REG_OFFSET(SDMA3, 0, in get_sdma_base_addr()
85 SOC15_REG_OFFSET(SDMA4, 0, in get_sdma_base_addr()
87 SOC15_REG_OFFSET(SDMA5, 0, in get_sdma_base_addr()
89 SOC15_REG_OFFSET(SDMA6, 0, in get_sdma_base_addr()
91 SOC15_REG_OFFSET(SDMA7, 0, in get_sdma_base_addr()
Dnbio_v6_1.c61 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in nbio_v6_1_hdp_flush()
73 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : in nbio_v6_1_sdma_doorbell_range()
74 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); in nbio_v6_1_sdma_doorbell_range()
211 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); in nbio_v6_1_get_hdp_flush_req_offset()
216 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); in nbio_v6_1_get_hdp_flush_done_offset()
221 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v6_1_get_pcie_index_offset()
226 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v6_1_get_pcie_data_offset()
Dnbio_v7_0.c80 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : in nbio_v7_0_sdma_doorbell_range()
81 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); in nbio_v7_0_sdma_doorbell_range()
97 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); in nbio_v7_0_vcn_doorbell_range()
250 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); in nbio_v7_0_get_hdp_flush_req_offset()
255 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); in nbio_v7_0_get_hdp_flush_done_offset()
260 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v7_0_get_pcie_index_offset()
265 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v7_0_get_pcie_data_offset()
Dvcn_v2_5.c176 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
178 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
180 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
182 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
184 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
187 adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH); in vcn_v2_5_sw_init()
622 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v2_5_start()
653 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0, in jpeg_v2_5_start()
657 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN), in jpeg_v2_5_start()
693 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), in jpeg_v2_5_stop()
[all …]
Dgfxhub_v2_0.c348 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
351 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
354 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); in gfxhub_v2_0_init()
356 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); in gfxhub_v2_0_init()
358 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_0_init()
360 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); in gfxhub_v2_0_init()
362 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_init()
Dgfxhub_v1_0.c363 SOC15_REG_OFFSET(GC, 0, in gfxhub_v1_0_init()
366 SOC15_REG_OFFSET(GC, 0, in gfxhub_v1_0_init()
369 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); in gfxhub_v1_0_init()
371 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); in gfxhub_v1_0_init()
373 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_init()
375 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); in gfxhub_v1_0_init()
377 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_0_init()
Dmxgpu_ai.h63 #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) *…
64 #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) *…
Dvcn_v2_0.c177 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v2_0_sw_init()
179 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_0_sw_init()
181 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_0_sw_init()
183 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_0_sw_init()
185 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v2_0_sw_init()
208 adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); in vcn_v2_0_sw_init()
674 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); in jpeg_v2_0_start()
686 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; in jpeg_v2_0_start()
687 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); in jpeg_v2_0_start()
705 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0, in jpeg_v2_0_start()
[all …]
Dvega10_ih.c386 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_get_wptr()
388 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in vega10_ih_get_wptr()
390 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); in vega10_ih_get_wptr()
411 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_get_wptr()
413 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_get_wptr()
415 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_get_wptr()
484 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_irq_rearm()
486 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in vega10_ih_irq_rearm()
488 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); in vega10_ih_irq_rearm()
Dmmhub_v2_0.c339 SOC15_REG_OFFSET(MMHUB, 0, in mmhub_v2_0_init()
342 SOC15_REG_OFFSET(MMHUB, 0, in mmhub_v2_0_init()
345 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); in mmhub_v2_0_init()
347 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); in mmhub_v2_0_init()
349 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_init()
351 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); in mmhub_v2_0_init()
353 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_0_init()
Dmmhub_v1_0.c416 SOC15_REG_OFFSET(MMHUB, 0, in mmhub_v1_0_init()
419 SOC15_REG_OFFSET(MMHUB, 0, in mmhub_v1_0_init()
422 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); in mmhub_v1_0_init()
424 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); in mmhub_v1_0_init()
426 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_init()
428 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); in mmhub_v1_0_init()
430 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v1_0_init()

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