168 	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);  in soc15_uvd_ctx_rreg()
169 	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);  in soc15_uvd_ctx_rreg()
182 	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);  in soc15_uvd_ctx_wreg()
183 	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);  in soc15_uvd_ctx_wreg()
196 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);  in soc15_didt_rreg()
197 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);  in soc15_didt_rreg()
210 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);  in soc15_didt_wreg()
211 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);  in soc15_didt_wreg()
315 	WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);  in soc15_read_bios_from_rom()
318 		dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));  in soc15_read_bios_from_rom()
369 		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))  in soc15_get_register_value()
371 		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))  in soc15_get_register_value()
430 		if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||  in soc15_program_register_sequence()
431 			reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||  in soc15_program_register_sequence()
432 			reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||  in soc15_program_register_sequence()
433 			reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))  in soc15_program_register_sequence()
797 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(  in soc15_invalidate_hdp()
1325 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));  in soc15_update_hdp_light_sleep()
1339 			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);  in soc15_update_hdp_light_sleep()
1341 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));  in soc15_update_hdp_light_sleep()
1349 			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);  in soc15_update_hdp_light_sleep()
1357 	def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));  in soc15_update_drm_clock_gating()
1379 		WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);  in soc15_update_drm_clock_gating()
1386 	def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));  in soc15_update_drm_light_sleep()
1394 		WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);  in soc15_update_drm_light_sleep()
1402 	def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));  in soc15_update_rom_medium_grain_clock_gating()
1412 		WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);  in soc15_update_rom_medium_grain_clock_gating()
1478 	data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));  in soc15_common_get_clockgating_state()
1483 	data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));  in soc15_common_get_clockgating_state()
1488 	data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));  in soc15_common_get_clockgating_state()
1493 	data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));  in soc15_common_get_clockgating_state()