1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "umc_v6_1.h"
24 #include "amdgpu_ras.h"
25 #include "amdgpu.h"
26
27 #include "rsmu/rsmu_0_0_2_offset.h"
28 #include "rsmu/rsmu_0_0_2_sh_mask.h"
29 #include "umc/umc_6_1_1_offset.h"
30 #include "umc/umc_6_1_1_sh_mask.h"
31
32 #define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10
33
34 /*
35 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
36 * is the index of 8KB block
37 */
38 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5)
39 /* channel index is the index of 256B block */
40 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8)
41 /* offset in 256B block */
42 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL)
43
44 const uint32_t
45 umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
46 {2, 18, 11, 27}, {4, 20, 13, 29},
47 {1, 17, 8, 24}, {7, 23, 14, 30},
48 {10, 26, 3, 19}, {12, 28, 5, 21},
49 {9, 25, 0, 16}, {15, 31, 6, 22}
50 };
51
umc_v6_1_enable_umc_index_mode(struct amdgpu_device * adev,uint32_t umc_instance)52 static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
53 uint32_t umc_instance)
54 {
55 uint32_t rsmu_umc_index;
56
57 rsmu_umc_index = RREG32_SOC15(RSMU, 0,
58 mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
59 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
60 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
61 RSMU_UMC_INDEX_MODE_EN, 1);
62 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
63 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
64 RSMU_UMC_INDEX_INSTANCE, umc_instance);
65 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
66 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
67 RSMU_UMC_INDEX_WREN, 1 << umc_instance);
68 WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
69 rsmu_umc_index);
70 }
71
umc_v6_1_disable_umc_index_mode(struct amdgpu_device * adev)72 static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
73 {
74 WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
75 RSMU_UMC_INDEX_MODE_EN, 0);
76 }
77
umc_v6_1_query_correctable_error_count(struct amdgpu_device * adev,uint32_t umc_reg_offset,unsigned long * error_count)78 static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
79 uint32_t umc_reg_offset,
80 unsigned long *error_count)
81 {
82 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
83 uint32_t ecc_err_cnt, ecc_err_cnt_addr;
84 uint64_t mc_umc_status;
85 uint32_t mc_umc_status_addr;
86
87 ecc_err_cnt_sel_addr =
88 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
89 ecc_err_cnt_addr =
90 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
91 mc_umc_status_addr =
92 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
93
94 /* select the lower chip and check the error count */
95 ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
96 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
97 EccErrCntCsSel, 0);
98 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
99 ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
100 *error_count +=
101 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
102 UMC_V6_1_CE_CNT_INIT);
103 /* clear the lower chip err count */
104 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
105
106 /* select the higher chip and check the err counter */
107 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
108 EccErrCntCsSel, 1);
109 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
110 ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
111 *error_count +=
112 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
113 UMC_V6_1_CE_CNT_INIT);
114 /* clear the higher chip err count */
115 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
116
117 /* check for SRAM correctable error
118 MCUMC_STATUS is a 64 bit register */
119 mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
120 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
121 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
122 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
123 *error_count += 1;
124 }
125
umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device * adev,uint32_t umc_reg_offset,unsigned long * error_count)126 static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev,
127 uint32_t umc_reg_offset,
128 unsigned long *error_count)
129 {
130 uint64_t mc_umc_status;
131 uint32_t mc_umc_status_addr;
132
133 mc_umc_status_addr =
134 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
135
136 /* check the MCUMC_STATUS */
137 mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
138 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
139 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
140 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
141 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
142 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
143 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
144 *error_count += 1;
145 }
146
umc_v6_1_query_error_count(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t umc_reg_offset,uint32_t channel_index)147 static void umc_v6_1_query_error_count(struct amdgpu_device *adev,
148 struct ras_err_data *err_data, uint32_t umc_reg_offset,
149 uint32_t channel_index)
150 {
151 umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
152 &(err_data->ce_count));
153 umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
154 &(err_data->ue_count));
155 }
156
umc_v6_1_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)157 static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
158 void *ras_error_status)
159 {
160 amdgpu_umc_for_each_channel(umc_v6_1_query_error_count);
161 }
162
umc_v6_1_query_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t umc_reg_offset,uint32_t channel_index)163 static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
164 struct ras_err_data *err_data,
165 uint32_t umc_reg_offset, uint32_t channel_index)
166 {
167 uint32_t lsb, mc_umc_status_addr;
168 uint64_t mc_umc_status, err_addr;
169
170 mc_umc_status_addr =
171 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
172
173 /* skip error address process if -ENOMEM */
174 if (!err_data->err_addr) {
175 /* clear umc status */
176 WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
177 return;
178 }
179
180 mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
181
182 /* calculate error address if ue/ce error is detected */
183 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
184 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
185 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
186 err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4);
187
188 /* the lowest lsb bits should be ignored */
189 lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB);
190 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
191 err_addr &= ~((0x1ULL << lsb) - 1);
192
193 /* translate umc channel address to soc pa, 3 parts are included */
194 err_data->err_addr[err_data->err_addr_cnt] =
195 ADDR_OF_8KB_BLOCK(err_addr) |
196 ADDR_OF_256B_BLOCK(channel_index) |
197 OFFSET_IN_256B_BLOCK(err_addr);
198
199 err_data->err_addr_cnt++;
200 }
201
202 /* clear umc status */
203 WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
204 }
205
umc_v6_1_query_ras_error_address(struct amdgpu_device * adev,void * ras_error_status)206 static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
207 void *ras_error_status)
208 {
209 amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
210 }
211
umc_v6_1_ras_init_per_channel(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t umc_reg_offset,uint32_t channel_index)212 static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev,
213 struct ras_err_data *err_data,
214 uint32_t umc_reg_offset, uint32_t channel_index)
215 {
216 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
217 uint32_t ecc_err_cnt_addr;
218
219 ecc_err_cnt_sel_addr =
220 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
221 ecc_err_cnt_addr =
222 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
223
224 /* select the lower chip and check the error count */
225 ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
226 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
227 EccErrCntCsSel, 0);
228 /* set ce error interrupt type to APIC based interrupt */
229 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
230 EccErrInt, 0x1);
231 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
232 /* set error count to initial value */
233 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
234
235 /* select the higher chip and check the err counter */
236 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
237 EccErrCntCsSel, 1);
238 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
239 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
240 }
241
umc_v6_1_ras_init(struct amdgpu_device * adev)242 static void umc_v6_1_ras_init(struct amdgpu_device *adev)
243 {
244 void *ras_error_status = NULL;
245
246 amdgpu_umc_for_each_channel(umc_v6_1_ras_init_per_channel);
247 }
248
249 const struct amdgpu_umc_funcs umc_v6_1_funcs = {
250 .ras_init = umc_v6_1_ras_init,
251 .query_ras_error_count = umc_v6_1_query_ras_error_count,
252 .query_ras_error_address = umc_v6_1_query_ras_error_address,
253 .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
254 .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode,
255 };
256
