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Searched refs:REG_READ (Results 1 – 25 of 89) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/gma500/
Dcdv_device.c36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
75 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
80 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
98 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
134 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
265 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()
[all …]
Dmdfld_intel_display.c64 temp = REG_READ(map->conf); in mdfldWaitForPipeDisable()
92 temp = REG_READ(map->conf); in mdfldWaitForPipeEnable()
106 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
124 dspcntr = REG_READ(dspcntr_reg); in mdfld__intel_plane_set_alpha()
193 dspcntr = REG_READ(map->cntr); in mdfld__intel_pipe_set_base()
216 REG_READ(map->linoff); in mdfld__intel_pipe_set_base()
218 REG_READ(map->surf); in mdfld__intel_pipe_set_base()
243 temp = REG_READ(map->cntr); in mdfld_disable_crtc()
248 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
249 REG_READ(map->base); in mdfld_disable_crtc()
[all …]
Dgma_display.c85 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
117 REG_READ(map->base); in gma_pipe_set_base()
120 REG_READ(map->base); in gma_pipe_set_base()
122 REG_READ(map->surf); in gma_pipe_set_base()
215 temp = REG_READ(map->dpll); in gma_crtc_dpms()
218 REG_READ(map->dpll); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
232 temp = REG_READ(map->cntr); in gma_crtc_dpms()
237 REG_WRITE(map->base, REG_READ(map->base)); in gma_crtc_dpms()
[all …]
Dcdv_intel_display.c133 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
151 *val = REG_READ(SB_DATA); in cdv_sb_read()
168 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
181 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
202 REG_READ(DPIO_CFG); in cdv_sb_reset()
469 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
472 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
473 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
481 REG_READ(OV_OVADD); in cdv_disable_sr()
[all …]
Dpsb_intel_lvds.c64 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
76 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
188 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
219 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
222 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
230 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
233 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
261 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
262 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
263 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
[all …]
Doaktrail_hdmi.c293 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
309 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
357 dspcntr = REG_READ(dspcntr_reg); in oaktrail_crtc_hdmi_mode_set()
363 pipeconf = REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
367 REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
370 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_mode_set()
393 temp = REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
396 REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
398 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); in oaktrail_crtc_hdmi_dpms()
399 REG_READ(DSPBSURF); in oaktrail_crtc_hdmi_dpms()
[all …]
Dpsb_lid.c28 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
30 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
34 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
44 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
46 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
Dpsb_intel_display.c82 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
191 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
215 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
224 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
245 REG_READ(LVDS); in psb_intel_crtc_mode_set()
250 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
257 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
282 REG_READ(map->conf); in psb_intel_crtc_mode_set()
311 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
313 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
[all …]
Dcdv_intel_dp.c391 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
395 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
405 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
409 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
424 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
429 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
431 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
432 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_on()
449 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
462 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
[all …]
Dmdfld_dsi_dpi.c48 (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { in mdfld_wait_for_HS_DATA_FIFO()
65 while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) in mdfld_wait_for_HS_CTRL_FIFO()
82 while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & in mdfld_wait_for_DPI_CTRL_FIFO()
100 while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) in mdfld_wait_for_SPL_PKG_SENT()
149 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
153 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
159 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
160 REG_READ(dspbase_reg); in dsi_set_pipe_plane_enable_state()
575 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
585 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
[all …]
Dintel_i2c.c29 val = REG_READ(chan->reg); in get_clock()
39 val = REG_READ(chan->reg); in get_data()
51 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
71 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
Dcdv_intel_crt.c45 temp = REG_READ(reg); in cdv_intel_crt_dpms()
108 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
148 orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN); in cdv_intel_crt_detect_hotplug()
162 if (!(REG_READ(PORT_HOTPLUG_EN) & in cdv_intel_crt_detect_hotplug()
169 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != in cdv_intel_crt_detect_hotplug()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_clk.c56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
/Linux-v5.4/drivers/net/wireless/ath/ath9k/
Dar9002_calib.c87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
[all …]
Dar9003_calib.c83 if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL) in ar9003_hw_per_calibration()
183 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9003_hw_iqcal_collect()
185 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9003_hw_iqcal_collect()
187 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9003_hw_iqcal_collect()
271 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
288 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
293 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
306 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); in ar9003_hw_iqcalibrate()
354 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
384 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
[all …]
Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA); in ath9k_hw_wow_set_arwr_reg()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); in ath9k_hw_wow_enable()
[all …]
Dar9002_mac.c43 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { in ar9002_hw_get_isr()
44 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9002_hw_get_isr()
46 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
50 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & in ar9002_hw_get_isr()
59 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
65 isr2 = REG_READ(ah, AR_ISR_S2); in ar9002_hw_get_isr()
88 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
109 s0_s = REG_READ(ah, AR_ISR_S0_S); in ar9002_hw_get_isr()
110 s1_s = REG_READ(ah, AR_ISR_S1_S); in ar9002_hw_get_isr()
112 s0_s = REG_READ(ah, AR_ISR_S0); in ar9002_hw_get_isr()
[all …]
Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
225 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
298 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
336 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
339 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
346 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
349 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
383 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
400 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
[all …]
Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
653 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
710 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ath9k_hw_stopdmarecv()
714 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
732 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
[all …]
Dar9003_mci.c39 if (!(REG_READ(ah, address) & bit_position)) { in ar9003_mci_wait_for_interrupt()
71 REG_READ(ah, AR_MCI_INTERRUPT_RAW), in ar9003_mci_wait_for_interrupt()
72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_wait_for_interrupt()
232 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); in ar9003_mci_prep_interface()
236 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_prep_interface()
238 REG_READ(ah, AR_MCI_INTERRUPT_RAW)); in ar9003_mci_prep_interface()
351 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_check_int()
375 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_get_isr()
376 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); in ar9003_mci_get_isr()
387 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS); in ar9003_mci_get_isr()
[all …]
Dar9003_phy.c626 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
644 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
669 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
712 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
730 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
1067 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1361 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1368 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1418 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1423 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubbub.c487 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
489 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
491 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
492 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
494 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); in hubbub2_wm_read_state()
498 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
500 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
502 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
503 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
505 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); in hubbub2_wm_read_state()
[all …]
/Linux-v5.4/drivers/net/wireless/ath/
Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; in ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_abm.c91 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); in calculate_16_bit_backlight_from_pwm()
95 bl_pwm_cntl = REG_READ(BL_PWM_CNTL); in calculate_16_bit_backlight_from_pwm()
234 s2 = REG_READ(BIOS_SCRATCH_2); in dmcu_set_backlight_level()
291 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); in dce_abm_get_current_backlight()
302 unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL); in dce_abm_get_target_backlight()
341 REG_READ(BL_PWM_CNTL); in dce_abm_immediate_disable()
343 REG_READ(BL_PWM_CNTL2); in dce_abm_immediate_disable()
345 REG_READ(BL_PWM_PERIOD_CNTL); in dce_abm_immediate_disable()
383 REG_READ(BL_PWM_CNTL); in dce_abm_init_backlight()
385 REG_READ(BL_PWM_CNTL2); in dce_abm_init_backlight()
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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubbub.c54 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub1_wm_read_state()
55 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); in hubbub1_wm_read_state()
57 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub1_wm_read_state()
58 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub1_wm_read_state()
60 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); in hubbub1_wm_read_state()
64 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub1_wm_read_state()
65 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); in hubbub1_wm_read_state()
67 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub1_wm_read_state()
68 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub1_wm_read_state()
70 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); in hubbub1_wm_read_state()
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