48 		(REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) {  in mdfld_wait_for_HS_DATA_FIFO()
65 	while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg)  in mdfld_wait_for_HS_CTRL_FIFO()
82 	while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) &  in mdfld_wait_for_DPI_CTRL_FIFO()
100 	while ((timeout < 20000) && (!(REG_READ(intr_stat_reg)  in mdfld_wait_for_SPL_PKG_SENT()
149 		REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */  in dsi_set_pipe_plane_enable_state()
153 		REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */  in dsi_set_pipe_plane_enable_state()
159 		REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));  in dsi_set_pipe_plane_enable_state()
160 		REG_READ(dspbase_reg);  in dsi_set_pipe_plane_enable_state()
575 	if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT)  in mdfld_dsi_dpi_turn_on()
585 	if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT)  in mdfld_dsi_dpi_turn_on()
614 	if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT)  in mdfld_dsi_dpi_shut_down()
618 	if (REG_READ(MIPI_DPI_CONTROL_REG(pipe)) == DSI_DPI_CTRL_HS_SHUTDOWN)  in mdfld_dsi_dpi_shut_down()
658 				REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31));  in mdfld_dsi_dpi_set_power()
659 			REG_READ(MIPI_PORT_CONTROL(pipe));  in mdfld_dsi_dpi_set_power()
675 				REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31));  in mdfld_dsi_dpi_set_power()
676 			REG_READ(MIPI_PORT_CONTROL(pipe));  in mdfld_dsi_dpi_set_power()
892 	REG_READ(MIPI_PORT_CONTROL(pipe));  in mdfld_dsi_dpi_mode_set()
910 	REG_READ(pipeconf_reg);  in mdfld_dsi_dpi_mode_set()
914 	REG_READ(dspcntr_reg);  in mdfld_dsi_dpi_mode_set()