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Searched refs:POSTING_READ (Results 1 – 25 of 26) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_hdmi.c236 POSTING_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
309 POSTING_READ(reg); in ibx_write_infoframe()
389 POSTING_READ(reg); in cpt_write_infoframe()
462 POSTING_READ(reg); in vlv_write_infoframe()
534 POSTING_READ(ctl_reg); in hsw_write_infoframe()
871 POSTING_READ(reg); in g4x_set_infoframes()
890 POSTING_READ(reg); in g4x_set_infoframes()
1042 POSTING_READ(reg); in ibx_set_infoframes()
1063 POSTING_READ(reg); in ibx_set_infoframes()
1099 POSTING_READ(reg); in cpt_set_infoframes()
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Dintel_fifo_underrun.c103 POSTING_READ(reg); in i9xx_check_fifo_underruns()
122 POSTING_READ(reg); in i9xx_set_fifo_underrun_reporting()
154 POSTING_READ(GEN7_ERR_INT); in ivybridge_check_fifo_underruns()
220 POSTING_READ(SERR_INT); in cpt_check_pch_fifo_underruns()
Dintel_dpll_mgr.c423 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_enable()
432 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_enable()
442 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_disable()
507 POSTING_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
515 POSTING_READ(SPLL_CTL); in hsw_ddi_spll_enable()
527 POSTING_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
545 POSTING_READ(SPLL_CTL); in hsw_ddi_spll_disable()
998 POSTING_READ(DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1011 POSTING_READ(regs[id].cfgcr1); in skl_ddi_pll_enable()
1012 POSTING_READ(regs[id].cfgcr2); in skl_ddi_pll_enable()
[all …]
Dintel_pipe_crc.c619 POSTING_READ(PIPE_CRC_CTL(crtc->index)); in intel_crtc_set_crc_source()
654 POSTING_READ(PIPE_CRC_CTL(crtc->index)); in intel_crtc_enable_pipe_crc()
669 POSTING_READ(PIPE_CRC_CTL(crtc->index)); in intel_crtc_disable_pipe_crc()
Dintel_ddi.c1094 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1124 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1134 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1143 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1165 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1170 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1177 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1186 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
2812 POSTING_READ(ICL_DPCLKA_CFGCR0); in icl_map_plls_to_ports()
3160 POSTING_READ(DP_TP_CTL(port)); in intel_ddi_disable_fec_state()
[all …]
Dintel_dp.c780 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
783 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
786 POSTING_READ(intel_dp->output_reg); in vlv_power_sequencer_kick()
2583 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_on()
2645 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_off_sync()
2736 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
2744 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
2752 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
2797 POSTING_READ(pp_ctrl_reg); in edp_panel_off()
2839 POSTING_READ(pp_ctrl_reg); in _intel_edp_backlight_on()
[all …]
Dintel_panel.c917 POSTING_READ(BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
952 POSTING_READ(BLC_PWM_CPU_CTL2); in pch_enable_backlight()
966 POSTING_READ(BLC_PWM_PCH_CTL1); in pch_enable_backlight()
995 POSTING_READ(BLC_PWM_CTL); in i9xx_enable_backlight()
1038 POSTING_READ(BLC_PWM_CTL2); in i965_enable_backlight()
1070 POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
1117 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); in bxt_enable_backlight()
1148 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); in cnp_enable_backlight()
Dintel_display.c1382 POSTING_READ(DPLL(pipe)); in _vlv_enable_pll()
1404 POSTING_READ(DPLL_MD(pipe)); in vlv_enable_pll()
1471 POSTING_READ(DPLL_MD(pipe)); in chv_enable_pll()
1506 POSTING_READ(reg); in i9xx_enable_pll()
1524 POSTING_READ(reg); in i9xx_enable_pll()
1543 POSTING_READ(DPLL(pipe)); in i9xx_disable_pll()
1559 POSTING_READ(DPLL(pipe)); in vlv_disable_pll()
1576 POSTING_READ(DPLL(pipe)); in chv_disable_pll()
1838 POSTING_READ(reg); in intel_enable_pipe()
4468 POSTING_READ(reg); in intel_fdi_normal_train()
[all …]
Dintel_lvds.c319 POSTING_READ(lvds_encoder->reg); in intel_enable_lvds()
339 POSTING_READ(lvds_encoder->reg); in intel_disable_lvds()
Dintel_crt.c454 POSTING_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
917 POSTING_READ(crt->adpa_reg); in intel_crt_reset()
Dicl_dsi.c321 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
327 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
617 POSTING_READ(ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
Dintel_display_power.c4116 POSTING_READ(reg); in intel_dbuf_slice_set()
4172 POSTING_READ(DBUF_CTL_S2); in icl_dbuf_enable()
4191 POSTING_READ(DBUF_CTL_S2); in icl_dbuf_disable()
4294 POSTING_READ(D_COMP_BDW); in hsw_write_dcomp()
4328 POSTING_READ(LCPLL_CTL); in hsw_disable_lcpll()
4346 POSTING_READ(LCPLL_CTL); in hsw_disable_lcpll()
4373 POSTING_READ(LCPLL_CTL); in hsw_restore_lcpll()
Dvlv_dsi_pll.c514 POSTING_READ(BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
Dintel_cdclk.c968 POSTING_READ(DPLL_CTRL1); in skl_dpll0_enable()
1058 POSTING_READ(CDCLK_CTL); in skl_set_cdclk()
1073 POSTING_READ(CDCLK_CTL); in skl_set_cdclk()
Dintel_sdvo.c221 POSTING_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
228 POSTING_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
245 POSTING_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
248 POSTING_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
Dintel_tv.c1614 POSTING_READ(TV_DAC); in intel_tv_detect_type()
1643 POSTING_READ(TV_CTL); in intel_tv_detect_type()
Dvlv_dsi.c676 POSTING_READ(port_ctrl); in intel_dsi_port_enable()
695 POSTING_READ(port_ctrl); in intel_dsi_port_disable()
Dintel_fbc.c211 POSTING_READ(MSG_FBC_REND_STATE); in intel_fbc_recompress()
/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Daperture_gm.c148 POSTING_READ(fence_reg_lo); in intel_vgpu_write_fence()
152 POSTING_READ(fence_reg_lo); in intel_vgpu_write_fence()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_irq.c326 POSTING_READ(DEIMR); in ilk_update_display_irq()
532 POSTING_READ(GEN8_DE_PORT_IMR); in bdw_update_port_irq()
564 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
590 POSTING_READ(SDEIMR); in ibx_display_interrupt_update()
654 POSTING_READ(reg); in i915_enable_pipestat()
677 POSTING_READ(reg); in i915_disable_pipestat()
1299 POSTING_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
1318 POSTING_READ(reg); in ivybridge_parity_work()
3161 POSTING_READ(SDEIER); in ibx_irq_pre_postinstall()
3236 POSTING_READ(VLV_MASTER_IER); in valleyview_irq_reset()
[all …]
Dintel_csr.c283 POSTING_READ(DC_STATE_DEBUG); in gen9_set_dc_state_debugmask()
Dintel_pm.c378 POSTING_READ(FW_BLC_SELF_VLV); in _intel_set_memory_cxsr()
382 POSTING_READ(FW_BLC_SELF); in _intel_set_memory_cxsr()
391 POSTING_READ(DSPFW3); in _intel_set_memory_cxsr()
397 POSTING_READ(FW_BLC_SELF); in _intel_set_memory_cxsr()
408 POSTING_READ(INSTPM); in _intel_set_memory_cxsr()
975 POSTING_READ(DSPFW1); in g4x_write_wm_values()
1054 POSTING_READ(DSPFW1); in vlv_write_wm_values()
8493 POSTING_READ(ECR); in intel_init_emon()
8902 POSTING_READ(DSPSURF(pipe)); in g4x_disable_trickle_feed()
9183 POSTING_READ(GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
Di915_drv.h2440 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) macro
Di915_drv.c2477 POSTING_READ(VLV_GTLC_WAKE_CTRL); in vlv_allow_gt_wake()
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_ringbuffer.c569 POSTING_READ(hwsp); in set_hwsp()

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