1382 	POSTING_READ(DPLL(pipe));  in _vlv_enable_pll()
1404 	POSTING_READ(DPLL_MD(pipe));  in vlv_enable_pll()
1471 		POSTING_READ(DPLL_MD(pipe));  in chv_enable_pll()
1506 	POSTING_READ(reg);  in i9xx_enable_pll()
1524 		POSTING_READ(reg);  in i9xx_enable_pll()
1543 	POSTING_READ(DPLL(pipe));  in i9xx_disable_pll()
1559 	POSTING_READ(DPLL(pipe));  in vlv_disable_pll()
1576 	POSTING_READ(DPLL(pipe));  in chv_disable_pll()
1838 	POSTING_READ(reg);  in intel_enable_pipe()
4468 	POSTING_READ(reg);  in intel_fdi_normal_train()
4515 	POSTING_READ(reg);  in ironlake_fdi_link_train()
4550 	POSTING_READ(reg);  in ironlake_fdi_link_train()
4596 	POSTING_READ(reg);  in gen6_fdi_link_train()
4625 	POSTING_READ(reg);  in gen6_fdi_link_train()
4635 		POSTING_READ(reg);  in gen6_fdi_link_train()
4678 	POSTING_READ(reg);  in gen6_fdi_link_train()
4688 		POSTING_READ(reg);  in gen6_fdi_link_train()
4729 	POSTING_READ(reg);  in ivb_manual_fdi_link_train()
4771 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
4806 		POSTING_READ(reg);  in ivb_manual_fdi_link_train()
4847 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
4854 	POSTING_READ(reg);  in ironlake_fdi_pll_enable()
4863 		POSTING_READ(reg);  in ironlake_fdi_pll_enable()
4886 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
4894 	POSTING_READ(reg);  in ironlake_fdi_pll_disable()
4911 	POSTING_READ(reg);  in ironlake_fdi_disable()
4919 	POSTING_READ(reg);  in ironlake_fdi_disable()
4947 	POSTING_READ(reg);  in ironlake_fdi_disable()
5148 	POSTING_READ(SOUTH_CHICKEN1);  in cpt_set_fdi_bc_bifurcation()
5725 		POSTING_READ(IPS_CTL);  in hsw_disable_ips()
8335 	POSTING_READ(PIPECONF(crtc->pipe));  in i9xx_set_pipeconf()
9002 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
9018 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
9029 		POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
9043 			POSTING_READ(PCH_DREF_CONTROL);  in ironlake_init_pch_refclk()
9428 	POSTING_READ(PIPECONF(pipe));  in ironlake_set_pipeconf()
9447 	POSTING_READ(PIPECONF(cpu_transcoder));  in haswell_set_pipeconf()
15959 	POSTING_READ(vga_reg);  in i915_disable_vga()
16332 	POSTING_READ(DPLL(pipe));  in i830_enable_pipe()
16345 		POSTING_READ(DPLL(pipe));  in i830_enable_pipe()
16350 	POSTING_READ(PIPECONF(pipe));  in i830_enable_pipe()
16369 	POSTING_READ(PIPECONF(pipe));  in i830_disable_pipe()
16374 	POSTING_READ(DPLL(pipe));  in i830_disable_pipe()