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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 18 of 18) sorted by relevance

/Linux-v5.4/drivers/pinctrl/sh-pfc/
Dpfc-r8a77470.c2748 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2776 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2804 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2832 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2889 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2917 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2945 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2973 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
3001 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
[all …]
Dpfc-sh7734.c1825 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1862 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1898 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1935 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1973 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2009 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2051 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2096 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2133 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2171 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
[all …]
Dpfc-r8a7791.c5703 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5763 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5800 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5837 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5876 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5921 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5960 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
6001 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6043 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6087 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-emev2.c1609 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1629 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1643 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1657 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1683 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1704 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
Dpfc-r8a7790.c4956 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4993 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5031 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5061 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5095 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5129 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5167 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5204 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5240 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5282 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7778.c2265 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2321 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2366 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2419 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2462 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2506 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2552 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2604 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2644 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2685 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7779.c3379 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3418 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3457 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3504 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3556 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3605 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3652 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3691 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3729 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3773 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7794.c4859 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4914 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4955 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4991 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5033 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5069 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5106 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5153 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5191 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5227 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7792.c2399 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2458 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2517 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2566 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2613 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2655 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2696 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2739 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Dsh_pfc.h161 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ macro
730 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
Dpfc-r8a77995.c2766 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2799 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a7795-es1.c5214 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5242 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5270 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a7796.c5537 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5563 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5591 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77965.c5777 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5803 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5831 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a7795.c5569 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5595 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5623 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77990.c4930 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4959 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a77970.c2359 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Dpfc-r8a77980.c2801 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,