Lines Matching refs:PINMUX_CFG_REG_VAR
2748 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2776 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2804 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2832 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2889 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2917 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2945 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2973 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
3001 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
3029 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
3058 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
3090 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
3118 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
3147 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
3175 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
3203 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
3232 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3259 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3307 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3354 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,