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Searched refs:GC (Results 1 – 25 of 25) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v2_0.c36 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_0_get_fb_location()
46 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_0_get_mc_fb_offset()
54 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_0_init_gart_pt_regs()
57 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_0_init_gart_pt_regs()
65 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
67 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
70 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
72 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
81 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
82 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); in gfxhub_v2_0_init_system_aperture_regs()
[all …]
Dgfxhub_v1_0.c35 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; in gfxhub_v1_0_get_mc_fb_offset()
45 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v1_0_setup_vm_pt_regs()
48 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v1_0_setup_vm_pt_regs()
58 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
74 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
[all …]
Dgfx_v9_0.c503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
[all …]
Dgfx_v10_0.c94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
[all …]
Dmes_v10_1.c192 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
194 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
197 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_enable()
201 data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); in mes_v10_1_enable()
204 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data); in mes_v10_1_enable()
208 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
210 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
216 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
241 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); in mes_v10_1_load_microcode()
248 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_load_microcode()
[all …]
Damdgpu_amdkfd_gfx_v10.c230 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_program_sh_mem_settings()
231 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_program_sh_mem_settings()
300 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_init_interrupts()
338 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
381 value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); in kgd_hqd_load()
384 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); in kgd_hqd_load()
389 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load()
392 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load()
399 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_hqd_load()
428 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), in kgd_hqd_load()
[all …]
Damdgpu_amdkfd_gfx_v9.c141 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
142 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
220 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_gfx_v9_init_interrupts()
282 value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); in kgd_gfx_v9_hqd_load()
285 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); in kgd_gfx_v9_hqd_load()
290 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load()
293 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load()
300 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_gfx_v9_hqd_load()
329 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_hqd_load()
331 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_hqd_load()
[all …]
Dpsp_v10_0.c259 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); in psp_v10_0_sram_map()
260 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); in psp_v10_0_sram_map()
265 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); in psp_v10_0_sram_map()
266 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); in psp_v10_0_sram_map()
271 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); in psp_v10_0_sram_map()
272 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); in psp_v10_0_sram_map()
277 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v10_0_sram_map()
278 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v10_0_sram_map()
283 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); in psp_v10_0_sram_map()
284 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); in psp_v10_0_sram_map()
[all …]
Dsoc15.c196 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_rreg()
197 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_rreg()
210 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in soc15_didt_wreg()
211 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in soc15_didt_wreg()
225 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); in soc15_gc_cac_rreg()
226 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); in soc15_gc_cac_rreg()
236 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); in soc15_gc_cac_wreg()
237 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); in soc15_gc_cac_wreg()
247 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); in soc15_se_cac_rreg()
248 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); in soc15_se_cac_rreg()
[all …]
Dnv.c97 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in nv_didt_rreg()
98 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in nv_didt_rreg()
111 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); in nv_didt_wreg()
112 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); in nv_didt_wreg()
140 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); in nv_grbm_select()
162 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
163 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
164 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
165 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
166 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
[all …]
Dpsp_v12_0.c413 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); in psp_v12_0_sram_map()
414 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); in psp_v12_0_sram_map()
419 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); in psp_v12_0_sram_map()
420 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); in psp_v12_0_sram_map()
425 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); in psp_v12_0_sram_map()
426 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); in psp_v12_0_sram_map()
431 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v12_0_sram_map()
432 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v12_0_sram_map()
437 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); in psp_v12_0_sram_map()
438 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); in psp_v12_0_sram_map()
[all …]
Dpsp_v3_1.c491 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); in psp_v3_1_sram_map()
492 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); in psp_v3_1_sram_map()
497 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); in psp_v3_1_sram_map()
498 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); in psp_v3_1_sram_map()
503 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); in psp_v3_1_sram_map()
504 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); in psp_v3_1_sram_map()
509 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v3_1_sram_map()
510 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v3_1_sram_map()
515 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); in psp_v3_1_sram_map()
516 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); in psp_v3_1_sram_map()
[all …]
Dsdma_v5_0.c65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
[all …]
Dgfxhub_v1_1.c33 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
48 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
Dpsp_v11_0.c576 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); in psp_v11_0_sram_map()
577 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); in psp_v11_0_sram_map()
582 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); in psp_v11_0_sram_map()
583 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); in psp_v11_0_sram_map()
588 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); in psp_v11_0_sram_map()
589 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); in psp_v11_0_sram_map()
594 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); in psp_v11_0_sram_map()
595 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v11_0_sram_map()
600 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); in psp_v11_0_sram_map()
601 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); in psp_v11_0_sram_map()
[all …]
Damdgpu_discovery.c230 info = &bhdr->table_list[GC]; in amdgpu_discovery_init()
393 le16_to_cpu(bhdr->table_list[GC].offset)); in amdgpu_discovery_get_gfx_info()
/Linux-v5.4/fs/jffs2/
DTODO4 space it could take. Let GC flush the outstanding writes because the
9 - fine-tune the allocation / GC thresholds
27 closer to 100% or 0% clean, hence speeding up later GC progress dramatically.
DREADME.Locking95 GC thread locks it, sends the signal, then unlocks it - while the GC
/Linux-v5.4/Documentation/ABI/testing/
Dsysfs-fs-f2fs107 section, it can let GC move partial segment{s} of one section
108 in one GC cycle, so that dispersing heavy overhead GC to
222 Do background GC agressively
228 Controls sleep time of GC urgent mode
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_powertune.c945 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_cac_driving_se_didt_config()
960 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_cac_driving_se_didt_config()
996 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_didt_config()
1005 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_didt_config()
1057 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_se_edc_config()
1068 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_config()
1107 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_edc_config()
1116 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_edc_config()
1166 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_force_stall_config()
/Linux-v5.4/drivers/gpu/drm/amd/include/
Ddiscovery.h35 GC, enumerator
/Linux-v5.4/Documentation/filesystems/
Df2fs.txt289 to 1, background thread starts to do GC by given
362 migration_granularity For large-sized sections, F2FS can stop GC given
383 gc_idle_interval F2FS detects the GC thread is idle, given time
395 gc_pin_file_thresh This indicates how many GC can be failed for the
/Linux-v5.4/Documentation/media/v4l-drivers/
Dgspca-cardlist.rst166 sunplus 04f1:1001 JVC GC A50
/Linux-v5.4/Documentation/networking/
Dip-sysctl.txt192 passes. More entries, less time-to-live, less GC interval.
/Linux-v5.4/
DCREDITS2871 D: Author of mark-and-sweep GC integrated by Alan Cox