Lines Matching refs:GC
36 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_0_get_fb_location()
46 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_0_get_mc_fb_offset()
54 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_0_init_gart_pt_regs()
57 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_0_init_gart_pt_regs()
65 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
67 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
70 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
72 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
81 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
82 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); in gfxhub_v2_0_init_system_aperture_regs()
83 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); in gfxhub_v2_0_init_system_aperture_regs()
86 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v2_0_init_system_aperture_regs()
88 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v2_0_init_system_aperture_regs()
94 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v2_0_init_system_aperture_regs()
96 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in gfxhub_v2_0_init_system_aperture_regs()
100 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, in gfxhub_v2_0_init_system_aperture_regs()
102 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, in gfxhub_v2_0_init_system_aperture_regs()
105 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v2_0_init_system_aperture_regs()
115 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
127 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
135 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
146 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_0_init_cache_regs()
148 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_0_init_cache_regs()
151 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_0_init_cache_regs()
163 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_0_init_cache_regs()
168 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_0_init_cache_regs()
175 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_0_enable_system_domain()
178 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v2_0_enable_system_domain()
183 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, in gfxhub_v2_0_disable_identity_aperture()
185 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, in gfxhub_v2_0_disable_identity_aperture()
188 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, in gfxhub_v2_0_disable_identity_aperture()
190 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, in gfxhub_v2_0_disable_identity_aperture()
193 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); in gfxhub_v2_0_disable_identity_aperture()
194 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); in gfxhub_v2_0_disable_identity_aperture()
204 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); in gfxhub_v2_0_setup_vmid_config()
229 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); in gfxhub_v2_0_setup_vmid_config()
230 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); in gfxhub_v2_0_setup_vmid_config()
231 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); in gfxhub_v2_0_setup_vmid_config()
232 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, in gfxhub_v2_0_setup_vmid_config()
234 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, in gfxhub_v2_0_setup_vmid_config()
244 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, in gfxhub_v2_0_program_invalidation()
246 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, in gfxhub_v2_0_program_invalidation()
259 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, in gfxhub_v2_0_gart_enable()
261 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, in gfxhub_v2_0_gart_enable()
286 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0); in gfxhub_v2_0_gart_disable()
289 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_gart_disable()
293 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_gart_disable()
296 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
297 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_0_gart_disable()
310 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_set_fault_enable_default()
340 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v2_0_set_fault_enable_default()
348 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
351 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
354 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); in gfxhub_v2_0_init()
356 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); in gfxhub_v2_0_init()
358 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_0_init()
360 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); in gfxhub_v2_0_init()
362 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_init()