Lines Matching refs:GC
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
396 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
952 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_get_csb_buffer()
1112 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
1115 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); in wave_read_ind()
1122 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
1128 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); in wave_read_regs()
1209 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v10_0_gpu_early_init()
1519 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v10_0_select_se_sh()
1526 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); in gfx_v10_0_get_rb_active_bitmap()
1527 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); in gfx_v10_0_get_rb_active_bitmap()
1616 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v10_0_init_compute_vmid()
1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v10_0_init_compute_vmid()
1625 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); in gfx_v10_0_init_compute_vmid()
1626 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); in gfx_v10_0_init_compute_vmid()
1627 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); in gfx_v10_0_init_compute_vmid()
1628 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); in gfx_v10_0_init_compute_vmid()
1643 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v10_0_init_gds_vmid()
1644 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v10_0_init_gds_vmid()
1645 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); in gfx_v10_0_init_gds_vmid()
1646 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); in gfx_v10_0_init_gds_vmid()
1702 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); in gfx_v10_0_tcp_harvest()
1706 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); in gfx_v10_0_tcp_harvest()
1708 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); in gfx_v10_0_tcp_harvest()
1712 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); in gfx_v10_0_tcp_harvest()
1724 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | in gfx_v10_0_get_tcc_info()
1725 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); in gfx_v10_0_get_tcc_info()
1737 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v10_0_constants_init()
1753 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v10_0_constants_init()
1759 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); in gfx_v10_0_constants_init()
1774 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_enable_gui_idle_interrupt()
1785 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); in gfx_v10_0_enable_gui_idle_interrupt()
1791 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, in gfx_v10_0_init_csb()
1793 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, in gfx_v10_0_init_csb()
1795 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
1813 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_stop()
1816 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop()
1821 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v10_0_rlc_reset()
1823 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v10_0_rlc_reset()
1832 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_0_rlc_smu_handshake_cntl()
1846 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); in gfx_v10_0_rlc_smu_handshake_cntl()
1856 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v10_0_rlc_start()
1865 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); in gfx_v10_0_rlc_enable_srm()
1868 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); in gfx_v10_0_rlc_enable_srm()
1887 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, in gfx_v10_0_rlc_load_microcode()
1891 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, in gfx_v10_0_rlc_load_microcode()
1894 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v10_0_rlc_load_microcode()
1919 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v10_0_rlc_resume()
1922 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); in gfx_v10_0_rlc_resume()
2192 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); in gfx_v10_0_rlc_backdoor_autoload_enable()
2193 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); in gfx_v10_0_rlc_backdoor_autoload_enable()
2194 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); in gfx_v10_0_rlc_backdoor_autoload_enable()
2196 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); in gfx_v10_0_rlc_backdoor_autoload_enable()
2203 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_backdoor_autoload_enable()
2220 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2222 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2226 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2241 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2243 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2257 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2259 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2263 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2278 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2280 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2294 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
2296 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
2300 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
2315 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
2317 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
2331 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
2333 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
2337 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
2352 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
2354 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
2367 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); in gfx_v10_0_wait_for_rlc_autoload_complete()
2368 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); in gfx_v10_0_wait_for_rlc_autoload_complete()
2406 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v10_0_cp_gfx_enable()
2415 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
2454 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2456 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2460 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2475 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2480 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); in gfx_v10_0_cp_gfx_load_pfp_microcode()
2481 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, in gfx_v10_0_cp_gfx_load_pfp_microcode()
2483 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, in gfx_v10_0_cp_gfx_load_pfp_microcode()
2524 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_ce_microcode()
2526 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); in gfx_v10_0_cp_gfx_load_ce_microcode()
2530 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_ce_microcode()
2545 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); in gfx_v10_0_cp_gfx_load_ce_microcode()
2550 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, in gfx_v10_0_cp_gfx_load_ce_microcode()
2552 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, in gfx_v10_0_cp_gfx_load_ce_microcode()
2593 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_me_microcode()
2595 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); in gfx_v10_0_cp_gfx_load_me_microcode()
2599 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_me_microcode()
2614 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); in gfx_v10_0_cp_gfx_load_me_microcode()
2619 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, in gfx_v10_0_cp_gfx_load_me_microcode()
2621 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, in gfx_v10_0_cp_gfx_load_me_microcode()
2666 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, in gfx_v10_0_cp_gfx_start()
2668 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); in gfx_v10_0_cp_gfx_start()
2701 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_cp_gfx_start()
2740 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_cp_gfx_switch_pipe()
2743 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); in gfx_v10_0_cp_gfx_switch_pipe()
2751 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); in gfx_v10_0_cp_gfx_set_doorbell()
2761 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); in gfx_v10_0_cp_gfx_set_doorbell()
2764 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v10_0_cp_gfx_set_doorbell()
2766 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, in gfx_v10_0_cp_gfx_set_doorbell()
2779 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); in gfx_v10_0_cp_gfx_resume()
2782 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); in gfx_v10_0_cp_gfx_resume()
2796 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
2800 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
2801 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
2805 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v10_0_cp_gfx_resume()
2806 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v10_0_cp_gfx_resume()
2810 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, in gfx_v10_0_cp_gfx_resume()
2812 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, in gfx_v10_0_cp_gfx_resume()
2816 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
2819 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); in gfx_v10_0_cp_gfx_resume()
2820 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v10_0_cp_gfx_resume()
2822 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); in gfx_v10_0_cp_gfx_resume()
2834 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
2837 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
2838 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
2841 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v10_0_cp_gfx_resume()
2842 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v10_0_cp_gfx_resume()
2845 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, in gfx_v10_0_cp_gfx_resume()
2847 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, in gfx_v10_0_cp_gfx_resume()
2851 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); in gfx_v10_0_cp_gfx_resume()
2854 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); in gfx_v10_0_cp_gfx_resume()
2855 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); in gfx_v10_0_cp_gfx_resume()
2856 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); in gfx_v10_0_cp_gfx_resume()
2881 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v10_0_cp_compute_enable()
2883 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, in gfx_v10_0_cp_compute_enable()
2914 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_cp_compute_load_microcode()
2916 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); in gfx_v10_0_cp_compute_load_microcode()
2920 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_cp_compute_load_microcode()
2935 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); in gfx_v10_0_cp_compute_load_microcode()
2939 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v10_0_cp_compute_load_microcode()
2941 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & in gfx_v10_0_cp_compute_load_microcode()
2943 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, in gfx_v10_0_cp_compute_load_microcode()
2947 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v10_0_cp_compute_load_microcode()
2950 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, in gfx_v10_0_cp_compute_load_microcode()
2953 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v10_0_cp_compute_load_microcode()
2969 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); in gfx_v10_0_kiq_setting()
2972 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); in gfx_v10_0_kiq_setting()
2974 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); in gfx_v10_0_kiq_setting()
2994 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); in gfx_v10_0_gfx_mqd_init()
3001 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); in gfx_v10_0_gfx_mqd_init()
3007 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); in gfx_v10_0_gfx_mqd_init()
3012 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); in gfx_v10_0_gfx_mqd_init()
3034 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); in gfx_v10_0_gfx_mqd_init()
3043 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); in gfx_v10_0_gfx_mqd_init()
3056 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); in gfx_v10_0_gfx_mqd_init()
3071 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); in gfx_v10_0_gfx_queue_init_register()
3072 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); in gfx_v10_0_gfx_queue_init_register()
3075 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); in gfx_v10_0_gfx_queue_init_register()
3076 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in gfx_v10_0_gfx_queue_init_register()
3079 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); in gfx_v10_0_gfx_queue_init_register()
3082 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); in gfx_v10_0_gfx_queue_init_register()
3084 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, in gfx_v10_0_gfx_queue_init_register()
3086 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); in gfx_v10_0_gfx_queue_init_register()
3089 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); in gfx_v10_0_gfx_queue_init_register()
3090 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); in gfx_v10_0_gfx_queue_init_register()
3093 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); in gfx_v10_0_gfx_queue_init_register()
3094 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); in gfx_v10_0_gfx_queue_init_register()
3097 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); in gfx_v10_0_gfx_queue_init_register()
3100 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); in gfx_v10_0_gfx_queue_init_register()
3101 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); in gfx_v10_0_gfx_queue_init_register()
3104 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); in gfx_v10_0_gfx_queue_init_register()
3107 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); in gfx_v10_0_gfx_queue_init_register()
3239 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); in gfx_v10_0_compute_mqd_init()
3246 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v10_0_compute_mqd_init()
3276 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in gfx_v10_0_compute_mqd_init()
3286 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); in gfx_v10_0_compute_mqd_init()
3314 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v10_0_compute_mqd_init()
3330 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); in gfx_v10_0_compute_mqd_init()
3335 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); in gfx_v10_0_compute_mqd_init()
3340 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); in gfx_v10_0_compute_mqd_init()
3357 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v10_0_kiq_init_register()
3360 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, in gfx_v10_0_kiq_init_register()
3362 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, in gfx_v10_0_kiq_init_register()
3366 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, in gfx_v10_0_kiq_init_register()
3370 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v10_0_kiq_init_register()
3374 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { in gfx_v10_0_kiq_init_register()
3375 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v10_0_kiq_init_register()
3377 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v10_0_kiq_init_register()
3381 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v10_0_kiq_init_register()
3383 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, in gfx_v10_0_kiq_init_register()
3385 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in gfx_v10_0_kiq_init_register()
3387 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v10_0_kiq_init_register()
3392 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, in gfx_v10_0_kiq_init_register()
3394 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, in gfx_v10_0_kiq_init_register()
3398 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, in gfx_v10_0_kiq_init_register()
3402 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, in gfx_v10_0_kiq_init_register()
3404 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, in gfx_v10_0_kiq_init_register()
3408 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, in gfx_v10_0_kiq_init_register()
3412 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v10_0_kiq_init_register()
3414 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v10_0_kiq_init_register()
3418 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v10_0_kiq_init_register()
3420 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v10_0_kiq_init_register()
3425 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v10_0_kiq_init_register()
3427 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v10_0_kiq_init_register()
3431 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v10_0_kiq_init_register()
3435 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in gfx_v10_0_kiq_init_register()
3437 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v10_0_kiq_init_register()
3441 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v10_0_kiq_init_register()
3443 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, in gfx_v10_0_kiq_init_register()
3447 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, in gfx_v10_0_kiq_init_register()
3451 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v10_0_kiq_init_register()
3650 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); in gfx_v10_0_check_grbm_cam_remapping()
3652 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); in gfx_v10_0_check_grbm_cam_remapping()
3654 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); in gfx_v10_0_check_grbm_cam_remapping()
3656 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { in gfx_v10_0_check_grbm_cam_remapping()
3657 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); in gfx_v10_0_check_grbm_cam_remapping()
3660 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); in gfx_v10_0_check_grbm_cam_remapping()
3671 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3674 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << in gfx_v10_0_setup_grbm_cam_remapping()
3676 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << in gfx_v10_0_setup_grbm_cam_remapping()
3678 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3679 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); in gfx_v10_0_setup_grbm_cam_remapping()
3682 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << in gfx_v10_0_setup_grbm_cam_remapping()
3684 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << in gfx_v10_0_setup_grbm_cam_remapping()
3686 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3687 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); in gfx_v10_0_setup_grbm_cam_remapping()
3690 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << in gfx_v10_0_setup_grbm_cam_remapping()
3692 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << in gfx_v10_0_setup_grbm_cam_remapping()
3694 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3695 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); in gfx_v10_0_setup_grbm_cam_remapping()
3698 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << in gfx_v10_0_setup_grbm_cam_remapping()
3700 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << in gfx_v10_0_setup_grbm_cam_remapping()
3702 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3703 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); in gfx_v10_0_setup_grbm_cam_remapping()
3706 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << in gfx_v10_0_setup_grbm_cam_remapping()
3708 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << in gfx_v10_0_setup_grbm_cam_remapping()
3710 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3711 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); in gfx_v10_0_setup_grbm_cam_remapping()
3714 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << in gfx_v10_0_setup_grbm_cam_remapping()
3716 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << in gfx_v10_0_setup_grbm_cam_remapping()
3718 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3719 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); in gfx_v10_0_setup_grbm_cam_remapping()
3722 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << in gfx_v10_0_setup_grbm_cam_remapping()
3724 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << in gfx_v10_0_setup_grbm_cam_remapping()
3726 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); in gfx_v10_0_setup_grbm_cam_remapping()
3727 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); in gfx_v10_0_setup_grbm_cam_remapping()
3845 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), in gfx_v10_0_is_idle()
3860 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & in gfx_v10_0_wait_for_idle()
3877 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); in gfx_v10_0_soft_reset()
3899 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); in gfx_v10_0_soft_reset()
3916 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_soft_reset()
3919 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v10_0_soft_reset()
3920 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_soft_reset()
3925 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); in gfx_v10_0_soft_reset()
3926 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); in gfx_v10_0_soft_reset()
3940 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); in gfx_v10_0_get_gpu_clock_counter()
3941 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v10_0_get_gpu_clock_counter()
3942 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v10_0_get_gpu_clock_counter()
3957 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, in gfx_v10_0_ring_emit_gds_switch()
3962 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, in gfx_v10_0_ring_emit_gds_switch()
3967 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, in gfx_v10_0_ring_emit_gds_switch()
3972 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, in gfx_v10_0_ring_emit_gds_switch()
4013 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_is_rlc_enabled()
4024 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); in gfx_v10_0_set_safe_mode()
4028 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) in gfx_v10_0_set_safe_mode()
4039 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); in gfx_v10_0_unset_safe_mode()
4050 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v10_0_update_medium_grain_clock_gating()
4059 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v10_0_update_medium_grain_clock_gating()
4065 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4068 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4072 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4075 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4080 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v10_0_update_medium_grain_clock_gating()
4086 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v10_0_update_medium_grain_clock_gating()
4089 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4092 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4096 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
4099 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
4112 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v10_0_update_3d_clock_gating()
4117 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v10_0_update_3d_clock_gating()
4119 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v10_0_update_3d_clock_gating()
4126 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v10_0_update_3d_clock_gating()
4129 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_3d_clock_gating()
4133 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_3d_clock_gating()
4136 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v10_0_update_3d_clock_gating()
4142 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v10_0_update_3d_clock_gating()
4152 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v10_0_update_coarse_grain_clock_gating()
4161 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v10_0_update_coarse_grain_clock_gating()
4164 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
4171 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
4174 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_coarse_grain_clock_gating()
4178 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
4180 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
4185 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
4285 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v10_0_get_clockgating_state()
4290 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_get_clockgating_state()
4299 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_get_clockgating_state()
4304 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_get_clockgating_state()
4309 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v10_0_get_clockgating_state()
4332 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v10_0_ring_get_wptr_gfx()
4333 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; in gfx_v10_0_ring_get_wptr_gfx()
4348 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_ring_set_wptr_gfx()
4349 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v10_0_ring_set_wptr_gfx()
4566 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); in gfx_v10_0_ring_emit_fence_kiq()
4823 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_set_gfx_eop_interrupt_state()
4826 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); in gfx_v10_0_set_gfx_eop_interrupt_state()
4870 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4873 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4876 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4879 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4993 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
5012 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_inst_fault_state()
5083 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
5085 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
5091 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
5094 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); in gfx_v10_0_kiq_set_interrupt_state()
5101 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()
5104 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); in gfx_v10_0_kiq_set_interrupt_state()
5358 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh()
5364 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); in gfx_v10_0_get_wgp_active_bitmap_per_sh()
5365 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v10_0_get_wgp_active_bitmap_per_sh()