Searched refs:DPLL (Results 1 – 14 of 14) sorted by relevance
| /Linux-v5.4/Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
39 - reg : offsets for the register set for controlling the DPLL.
49 - DPLL mode setting - defining any one or more of the following overrides
51 - ti,low-power-stop : DPLL supports low power stop mode, gating output
52 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
53 - ti,lock : DPLL locks in programmed rate
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| D | apll.txt | 11 a subtype of a DPLL [2], although a simplified one at that.
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| /Linux-v5.4/include/dt-bindings/clock/ |
| D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_dvo.c | 484 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
485 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
492 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
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| D | intel_display.c | 1095 val = I915_READ(DPLL(pipe)); in assert_pll()
1381 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1382 POSTING_READ(DPLL(pipe)); in _vlv_enable_pll()
1385 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1431 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1434 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1468 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
1487 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1542 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1543 POSTING_READ(DPLL(pipe)); in i9xx_disable_pll()
[all …]
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| D | intel_display_power.c | 1181 u32 val = I915_READ(DPLL(pipe)); in vlv_display_power_well_init()
1187 I915_WRITE(DPLL(pipe), val); in vlv_display_power_well_init()
1341 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
4759 u32 status = I915_READ(DPLL(PIPE_A)); in chv_phy_control_init()
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| D | intel_dp.c | 755 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
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| /Linux-v5.4/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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| /Linux-v5.4/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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| /Linux-v5.4/Documentation/arm/omap/ |
| D | dss.rst | 32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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| /Linux-v5.4/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| D | reg.h | 256 #define DPLL 0x034A macro
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | rk3036.dtsi | 216 * Fix the emac parent clock is DPLL instead of APLL.
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| /Linux-v5.4/Documentation/networking/ |
| D | z8530drv.txt | 291 present at all (BayCom). It feeds back the output of the DPLL
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 3257 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro
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