1095 	val = I915_READ(DPLL(pipe));  in assert_pll()
1381 	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);  in _vlv_enable_pll()
1382 	POSTING_READ(DPLL(pipe));  in _vlv_enable_pll()
1385 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))  in _vlv_enable_pll()
1431 	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);  in _chv_enable_pll()
1434 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))  in _chv_enable_pll()
1468 		WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);  in chv_enable_pll()
1487 	i915_reg_t reg = DPLL(crtc->pipe);  in i9xx_enable_pll()
1542 	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);  in i9xx_disable_pll()
1543 	POSTING_READ(DPLL(pipe));  in i9xx_disable_pll()
1558 	I915_WRITE(DPLL(pipe), val);  in vlv_disable_pll()
1559 	POSTING_READ(DPLL(pipe));  in vlv_disable_pll()
1575 	I915_WRITE(DPLL(pipe), val);  in chv_disable_pll()
1576 	POSTING_READ(DPLL(pipe));  in chv_disable_pll()
1598 		dpll_reg = DPLL(0);  in vlv_wait_port_ready()
1602 		dpll_reg = DPLL(0);  in vlv_wait_port_ready()
7748 	I915_WRITE(DPLL(pipe),  in vlv_prepare_pll()
7850 	I915_WRITE(DPLL(pipe),  in chv_prepare_pll()
8840 		tmp = I915_READ(DPLL(crtc->pipe));  in i9xx_get_pipe_config()
8850 	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));  in i9xx_get_pipe_config()
16328 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);  in i830_enable_pipe()
16329 	I915_WRITE(DPLL(pipe), dpll);  in i830_enable_pipe()
16332 	POSTING_READ(DPLL(pipe));  in i830_enable_pipe()
16340 	I915_WRITE(DPLL(pipe), dpll);  in i830_enable_pipe()
16344 		I915_WRITE(DPLL(pipe), dpll);  in i830_enable_pipe()
16345 		POSTING_READ(DPLL(pipe));  in i830_enable_pipe()
16373 	I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);  in i830_disable_pipe()
16374 	POSTING_READ(DPLL(pipe));  in i830_disable_pipe()