1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3036-cru.h> 8#include <dt-bindings/soc/rockchip,boot-mode.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 compatible = "rockchip,rk3036"; 15 16 interrupt-parent = <&gic>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 mshc0 = &emmc; 23 mshc1 = &sdmmc; 24 mshc2 = &sdio; 25 serial0 = &uart0; 26 serial1 = &uart1; 27 serial2 = &uart2; 28 spi = &spi; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 enable-method = "rockchip,rk3036-smp"; 35 36 cpu0: cpu@f00 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a7"; 39 reg = <0xf00>; 40 resets = <&cru SRST_CORE0>; 41 operating-points = < 42 /* KHz uV */ 43 816000 1000000 44 >; 45 clock-latency = <40000>; 46 clocks = <&cru ARMCLK>; 47 }; 48 49 cpu1: cpu@f01 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a7"; 52 reg = <0xf01>; 53 resets = <&cru SRST_CORE1>; 54 }; 55 }; 56 57 amba { 58 compatible = "simple-bus"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 pdma: pdma@20078000 { 64 compatible = "arm,pl330", "arm,primecell"; 65 reg = <0x20078000 0x4000>; 66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 68 #dma-cells = <1>; 69 arm,pl330-broken-no-flushp; 70 clocks = <&cru ACLK_DMAC2>; 71 clock-names = "apb_pclk"; 72 }; 73 }; 74 75 arm-pmu { 76 compatible = "arm,cortex-a7-pmu"; 77 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-affinity = <&cpu0>, <&cpu1>; 80 }; 81 82 display-subsystem { 83 compatible = "rockchip,display-subsystem"; 84 ports = <&vop_out>; 85 }; 86 87 timer { 88 compatible = "arm,armv7-timer"; 89 arm,cpu-registers-not-fw-configured; 90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 94 clock-frequency = <24000000>; 95 }; 96 97 xin24m: oscillator { 98 compatible = "fixed-clock"; 99 clock-frequency = <24000000>; 100 clock-output-names = "xin24m"; 101 #clock-cells = <0>; 102 }; 103 104 bus_intmem@10080000 { 105 compatible = "mmio-sram"; 106 reg = <0x10080000 0x2000>; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0x10080000 0x2000>; 110 111 smp-sram@0 { 112 compatible = "rockchip,rk3066-smp-sram"; 113 reg = <0x00 0x10>; 114 }; 115 }; 116 117 gpu: gpu@10090000 { 118 compatible = "rockchip,rk3036-mali", "arm,mali-400"; 119 reg = <0x10090000 0x10000>; 120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 124 interrupt-names = "gp", 125 "gpmmu", 126 "pp0", 127 "ppmmu0"; 128 assigned-clocks = <&cru SCLK_GPU>; 129 assigned-clock-rates = <100000000>; 130 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 131 clock-names = "core", "bus"; 132 resets = <&cru SRST_GPU>; 133 status = "disabled"; 134 }; 135 136 vop: vop@10118000 { 137 compatible = "rockchip,rk3036-vop"; 138 reg = <0x10118000 0x19c>; 139 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; 141 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 142 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; 143 reset-names = "axi", "ahb", "dclk"; 144 iommus = <&vop_mmu>; 145 status = "disabled"; 146 147 vop_out: port { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 vop_out_hdmi: endpoint@0 { 151 reg = <0>; 152 remote-endpoint = <&hdmi_in_vop>; 153 }; 154 }; 155 }; 156 157 vop_mmu: iommu@10118300 { 158 compatible = "rockchip,iommu"; 159 reg = <0x10118300 0x100>; 160 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 161 interrupt-names = "vop_mmu"; 162 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; 163 clock-names = "aclk", "iface"; 164 #iommu-cells = <0>; 165 status = "disabled"; 166 }; 167 168 gic: interrupt-controller@10139000 { 169 compatible = "arm,gic-400"; 170 interrupt-controller; 171 #interrupt-cells = <3>; 172 #address-cells = <0>; 173 174 reg = <0x10139000 0x1000>, 175 <0x1013a000 0x2000>, 176 <0x1013c000 0x2000>, 177 <0x1013e000 0x2000>; 178 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 179 }; 180 181 usb_otg: usb@10180000 { 182 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 183 "snps,dwc2"; 184 reg = <0x10180000 0x40000>; 185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&cru HCLK_OTG0>; 187 clock-names = "otg"; 188 dr_mode = "otg"; 189 g-np-tx-fifo-size = <16>; 190 g-rx-fifo-size = <275>; 191 g-tx-fifo-size = <256 128 128 64 64 32>; 192 status = "disabled"; 193 }; 194 195 usb_host: usb@101c0000 { 196 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 197 "snps,dwc2"; 198 reg = <0x101c0000 0x40000>; 199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&cru HCLK_OTG1>; 201 clock-names = "otg"; 202 dr_mode = "host"; 203 status = "disabled"; 204 }; 205 206 emac: ethernet@10200000 { 207 compatible = "rockchip,rk3036-emac", "snps,arc-emac"; 208 reg = <0x10200000 0x4000>; 209 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 rockchip,grf = <&grf>; 213 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; 214 clock-names = "hclk", "macref", "macclk"; 215 /* 216 * Fix the emac parent clock is DPLL instead of APLL. 217 * since that will cause some unstable things if the cpufreq 218 * is working. (e.g: the accurate 50MHz what mac_ref need) 219 */ 220 assigned-clocks = <&cru SCLK_MACPLL>; 221 assigned-clock-parents = <&cru PLL_DPLL>; 222 max-speed = <100>; 223 phy-mode = "rmii"; 224 status = "disabled"; 225 }; 226 227 sdmmc: dwmmc@10214000 { 228 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 229 reg = <0x10214000 0x4000>; 230 clock-frequency = <37500000>; 231 max-frequency = <37500000>; 232 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 233 clock-names = "biu", "ciu"; 234 fifo-depth = <0x100>; 235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 236 resets = <&cru SRST_MMC0>; 237 reset-names = "reset"; 238 status = "disabled"; 239 }; 240 241 sdio: dwmmc@10218000 { 242 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 243 reg = <0x10218000 0x4000>; 244 max-frequency = <37500000>; 245 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 246 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 248 fifo-depth = <0x100>; 249 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 250 resets = <&cru SRST_SDIO>; 251 reset-names = "reset"; 252 status = "disabled"; 253 }; 254 255 emmc: dwmmc@1021c000 { 256 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 257 reg = <0x1021c000 0x4000>; 258 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 259 bus-width = <8>; 260 cap-mmc-highspeed; 261 clock-frequency = <37500000>; 262 max-frequency = <37500000>; 263 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 264 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 265 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 266 default-sample-phase = <158>; 267 disable-wp; 268 dmas = <&pdma 12>; 269 dma-names = "rx-tx"; 270 fifo-depth = <0x100>; 271 mmc-ddr-1_8v; 272 non-removable; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 275 resets = <&cru SRST_EMMC>; 276 reset-names = "reset"; 277 status = "disabled"; 278 }; 279 280 i2s: i2s@10220000 { 281 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; 282 reg = <0x10220000 0x4000>; 283 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clock-names = "i2s_clk", "i2s_hclk"; 287 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; 288 dmas = <&pdma 0>, <&pdma 1>; 289 dma-names = "tx", "rx"; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&i2s_bus>; 292 #sound-dai-cells = <0>; 293 status = "disabled"; 294 }; 295 296 cru: clock-controller@20000000 { 297 compatible = "rockchip,rk3036-cru"; 298 reg = <0x20000000 0x1000>; 299 rockchip,grf = <&grf>; 300 #clock-cells = <1>; 301 #reset-cells = <1>; 302 assigned-clocks = <&cru PLL_GPLL>; 303 assigned-clock-rates = <594000000>; 304 }; 305 306 grf: syscon@20008000 { 307 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; 308 reg = <0x20008000 0x1000>; 309 310 reboot-mode { 311 compatible = "syscon-reboot-mode"; 312 offset = <0x1d8>; 313 mode-normal = <BOOT_NORMAL>; 314 mode-recovery = <BOOT_RECOVERY>; 315 mode-bootloader = <BOOT_FASTBOOT>; 316 mode-loader = <BOOT_BL_DOWNLOAD>; 317 }; 318 }; 319 320 acodec: acodec-ana@20030000 { 321 compatible = "rk3036-codec"; 322 reg = <0x20030000 0x4000>; 323 rockchip,grf = <&grf>; 324 clock-names = "acodec_pclk"; 325 clocks = <&cru PCLK_ACODEC>; 326 status = "disabled"; 327 }; 328 329 hdmi: hdmi@20034000 { 330 compatible = "rockchip,rk3036-inno-hdmi"; 331 reg = <0x20034000 0x4000>; 332 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru PCLK_HDMI>; 334 clock-names = "pclk"; 335 rockchip,grf = <&grf>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&hdmi_ctl>; 338 status = "disabled"; 339 340 hdmi_in: port { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 hdmi_in_vop: endpoint@0 { 344 reg = <0>; 345 remote-endpoint = <&vop_out_hdmi>; 346 }; 347 }; 348 }; 349 350 timer: timer@20044000 { 351 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; 352 reg = <0x20044000 0x20>; 353 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&xin24m>, <&cru PCLK_TIMER>; 355 clock-names = "timer", "pclk"; 356 }; 357 358 pwm0: pwm@20050000 { 359 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 360 reg = <0x20050000 0x10>; 361 #pwm-cells = <3>; 362 clocks = <&cru PCLK_PWM>; 363 clock-names = "pwm"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pwm0_pin>; 366 status = "disabled"; 367 }; 368 369 pwm1: pwm@20050010 { 370 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 371 reg = <0x20050010 0x10>; 372 #pwm-cells = <3>; 373 clocks = <&cru PCLK_PWM>; 374 clock-names = "pwm"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pwm1_pin>; 377 status = "disabled"; 378 }; 379 380 pwm2: pwm@20050020 { 381 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 382 reg = <0x20050020 0x10>; 383 #pwm-cells = <3>; 384 clocks = <&cru PCLK_PWM>; 385 clock-names = "pwm"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pwm2_pin>; 388 status = "disabled"; 389 }; 390 391 pwm3: pwm@20050030 { 392 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 393 reg = <0x20050030 0x10>; 394 #pwm-cells = <2>; 395 clocks = <&cru PCLK_PWM>; 396 clock-names = "pwm"; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pwm3_pin>; 399 status = "disabled"; 400 }; 401 402 i2c1: i2c@20056000 { 403 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 404 reg = <0x20056000 0x1000>; 405 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clock-names = "i2c"; 409 clocks = <&cru PCLK_I2C1>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&i2c1_xfer>; 412 status = "disabled"; 413 }; 414 415 i2c2: i2c@2005a000 { 416 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 417 reg = <0x2005a000 0x1000>; 418 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 clock-names = "i2c"; 422 clocks = <&cru PCLK_I2C2>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&i2c2_xfer>; 425 status = "disabled"; 426 }; 427 428 uart0: serial@20060000 { 429 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 430 reg = <0x20060000 0x100>; 431 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 432 reg-shift = <2>; 433 reg-io-width = <4>; 434 clock-frequency = <24000000>; 435 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 436 clock-names = "baudclk", "apb_pclk"; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 439 status = "disabled"; 440 }; 441 442 uart1: serial@20064000 { 443 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 444 reg = <0x20064000 0x100>; 445 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 446 reg-shift = <2>; 447 reg-io-width = <4>; 448 clock-frequency = <24000000>; 449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 450 clock-names = "baudclk", "apb_pclk"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&uart1_xfer>; 453 status = "disabled"; 454 }; 455 456 uart2: serial@20068000 { 457 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 458 reg = <0x20068000 0x100>; 459 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 460 reg-shift = <2>; 461 reg-io-width = <4>; 462 clock-frequency = <24000000>; 463 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 464 clock-names = "baudclk", "apb_pclk"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&uart2_xfer>; 467 status = "disabled"; 468 }; 469 470 i2c0: i2c@20072000 { 471 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 472 reg = <0x20072000 0x1000>; 473 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 clock-names = "i2c"; 477 clocks = <&cru PCLK_I2C0>; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&i2c0_xfer>; 480 status = "disabled"; 481 }; 482 483 spi: spi@20074000 { 484 compatible = "rockchip,rockchip-spi"; 485 reg = <0x20074000 0x1000>; 486 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>; 488 clock-names = "apb-pclk","spi_pclk"; 489 dmas = <&pdma 8>, <&pdma 9>; 490 dma-names = "tx", "rx"; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 pinctrl: pinctrl { 499 compatible = "rockchip,rk3036-pinctrl"; 500 rockchip,grf = <&grf>; 501 #address-cells = <1>; 502 #size-cells = <1>; 503 ranges; 504 505 gpio0: gpio0@2007c000 { 506 compatible = "rockchip,gpio-bank"; 507 reg = <0x2007c000 0x100>; 508 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru PCLK_GPIO0>; 510 511 gpio-controller; 512 #gpio-cells = <2>; 513 514 interrupt-controller; 515 #interrupt-cells = <2>; 516 }; 517 518 gpio1: gpio1@20080000 { 519 compatible = "rockchip,gpio-bank"; 520 reg = <0x20080000 0x100>; 521 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cru PCLK_GPIO1>; 523 524 gpio-controller; 525 #gpio-cells = <2>; 526 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 531 gpio2: gpio2@20084000 { 532 compatible = "rockchip,gpio-bank"; 533 reg = <0x20084000 0x100>; 534 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&cru PCLK_GPIO2>; 536 537 gpio-controller; 538 #gpio-cells = <2>; 539 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 }; 543 544 pcfg_pull_default: pcfg_pull_default { 545 bias-pull-pin-default; 546 }; 547 548 pcfg_pull_none: pcfg-pull-none { 549 bias-disable; 550 }; 551 552 pwm0 { 553 pwm0_pin: pwm0-pin { 554 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 555 }; 556 }; 557 558 pwm1 { 559 pwm1_pin: pwm1-pin { 560 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 561 }; 562 }; 563 564 pwm2 { 565 pwm2_pin: pwm2-pin { 566 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 567 }; 568 }; 569 570 pwm3 { 571 pwm3_pin: pwm3-pin { 572 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 573 }; 574 }; 575 576 sdmmc { 577 sdmmc_clk: sdmmc-clk { 578 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 579 }; 580 581 sdmmc_cmd: sdmmc-cmd { 582 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 583 }; 584 585 sdmmc_cd: sdmmc-cd { 586 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 587 }; 588 589 sdmmc_bus1: sdmmc-bus1 { 590 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; 591 }; 592 593 sdmmc_bus4: sdmmc-bus4 { 594 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 595 <1 RK_PC3 1 &pcfg_pull_default>, 596 <1 RK_PC4 1 &pcfg_pull_default>, 597 <1 RK_PC5 1 &pcfg_pull_default>; 598 }; 599 }; 600 601 sdio { 602 sdio_bus1: sdio-bus1 { 603 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; 604 }; 605 606 sdio_bus4: sdio-bus4 { 607 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, 608 <0 RK_PB4 1 &pcfg_pull_default>, 609 <0 RK_PB5 1 &pcfg_pull_default>, 610 <0 RK_PB6 1 &pcfg_pull_default>; 611 }; 612 613 sdio_cmd: sdio-cmd { 614 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; 615 }; 616 617 sdio_clk: sdio-clk { 618 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; 619 }; 620 }; 621 622 emmc { 623 /* 624 * We run eMMC at max speed; bump up drive strength. 625 * We also have external pulls, so disable the internal ones. 626 */ 627 emmc_clk: emmc-clk { 628 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 629 }; 630 631 emmc_cmd: emmc-cmd { 632 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; 633 }; 634 635 emmc_bus8: emmc-bus8 { 636 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 637 <1 RK_PD1 2 &pcfg_pull_default>, 638 <1 RK_PD2 2 &pcfg_pull_default>, 639 <1 RK_PD3 2 &pcfg_pull_default>, 640 <1 RK_PD4 2 &pcfg_pull_default>, 641 <1 RK_PD5 2 &pcfg_pull_default>, 642 <1 RK_PD6 2 &pcfg_pull_default>, 643 <1 RK_PD7 2 &pcfg_pull_default>; 644 }; 645 }; 646 647 emac { 648 emac_xfer: emac-xfer { 649 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ 650 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ 651 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ 652 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ 653 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ 654 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ 655 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ 656 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ 657 }; 658 659 emac_mdio: emac-mdio { 660 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ 661 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ 662 }; 663 }; 664 665 i2c0 { 666 i2c0_xfer: i2c0-xfer { 667 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 668 <0 RK_PA1 1 &pcfg_pull_none>; 669 }; 670 }; 671 672 i2c1 { 673 i2c1_xfer: i2c1-xfer { 674 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 675 <0 RK_PA3 1 &pcfg_pull_none>; 676 }; 677 }; 678 679 i2c2 { 680 i2c2_xfer: i2c2-xfer { 681 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 682 <2 RK_PC5 1 &pcfg_pull_none>; 683 }; 684 }; 685 686 i2s { 687 i2s_bus: i2s-bus { 688 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 689 <1 RK_PA1 1 &pcfg_pull_default>, 690 <1 RK_PA2 1 &pcfg_pull_default>, 691 <1 RK_PA3 1 &pcfg_pull_default>, 692 <1 RK_PA4 1 &pcfg_pull_default>, 693 <1 RK_PA5 1 &pcfg_pull_default>; 694 }; 695 }; 696 697 hdmi { 698 hdmi_ctl: hdmi-ctl { 699 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, 700 <1 RK_PB1 1 &pcfg_pull_none>, 701 <1 RK_PB2 1 &pcfg_pull_none>, 702 <1 RK_PB3 1 &pcfg_pull_none>; 703 }; 704 }; 705 706 uart0 { 707 uart0_xfer: uart0-xfer { 708 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 709 <0 RK_PC1 1 &pcfg_pull_none>; 710 }; 711 712 uart0_cts: uart0-cts { 713 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; 714 }; 715 716 uart0_rts: uart0-rts { 717 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; 718 }; 719 }; 720 721 uart1 { 722 uart1_xfer: uart1-xfer { 723 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, 724 <2 RK_PC7 1 &pcfg_pull_none>; 725 }; 726 /* no rts / cts for uart1 */ 727 }; 728 729 uart2 { 730 uart2_xfer: uart2-xfer { 731 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 732 <1 RK_PC3 2 &pcfg_pull_none>; 733 }; 734 /* no rts / cts for uart2 */ 735 }; 736 737 spi-pins { 738 spi_txd:spi-txd { 739 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 740 }; 741 742 spi_rxd:spi-rxd { 743 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 744 }; 745 746 spi_clk:spi-clk { 747 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 748 }; 749 750 spi_cs0:spi-cs0 { 751 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 752 753 }; 754 755 spi_cs1:spi-cs1 { 756 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 757 758 }; 759 }; 760 }; 761}; 762
