| /Linux-v5.4/include/dt-bindings/clock/ |
| D | sun50i-a64-ccu.h | 105 #define CLK_I2S2 84 macro
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| D | sun8i-a83t-ccu.h | 111 #define CLK_I2S2 74 macro
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| D | sun8i-h3-ccu.h | 119 #define CLK_I2S2 86 macro
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| D | sun50i-h6-ccu.h | 79 #define CLK_I2S2 93 macro
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| D | sun8i-r40-ccu.h | 143 #define CLK_I2S2 119 macro
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| D | sun4i-a10-ccu.h | 160 #define CLK_I2S2 129 macro
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| D | exynos5250.h | 111 #define CLK_I2S2 308 macro
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| D | s5pv210.h | 171 #define CLK_I2S2 153 macro
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| D | exynos5420.h | 85 #define CLK_I2S2 276 macro
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| D | exynos4.h | 169 #define CLK_I2S2 331 macro
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| /Linux-v5.4/drivers/clk/zte/ |
| D | clk-zx296702.c | 43 #define CLK_I2S2 (lsp0crpm_base + 0x34) macro
653 ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1); in zx296702_lsp0_clocks_init()
655 zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1); in zx296702_lsp0_clocks_init()
657 zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0); in zx296702_lsp0_clocks_init()
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| /Linux-v5.4/drivers/clk/sunxi-ng/ |
| D | ccu-sun8i-h3.c | 829 [CLK_I2S2] = &i2s2_clk.common.hw,
945 [CLK_I2S2] = &i2s2_clk.common.hw,
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| D | ccu-sun50i-a64.c | 821 [CLK_I2S2] = &i2s2_clk.common.hw,
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| D | ccu-sun8i-a83t.c | 769 [CLK_I2S2] = &i2s2_clk.common.hw,
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| D | ccu-sun50i-h6.c | 1021 [CLK_I2S2] = &i2s2_clk.common.hw,
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| D | ccu-sun8i-r40.c | 1100 [CLK_I2S2] = &i2s2_clk.common.hw,
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| D | ccu-sun4i-a10.c | 1337 [CLK_I2S2] = &i2s2_clk.common.hw,
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| /Linux-v5.4/drivers/clk/samsung/ |
| D | clk-s5pv210.c | 656 GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
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| D | clk-exynos5250.c | 592 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
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| D | clk-exynos4.c | 884 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
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| D | clk-exynos5420.c | 1080 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | s5pv210.dtsi | 294 clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
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| D | exynos4.dtsi | 428 clocks = <&clock CLK_I2S2>;
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| D | sun8i-a83t.dtsi | 875 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
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| D | exynos5250.dtsi | 627 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
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