1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
4 * Copyright (c) 2017 Maxime Ripard.
5 * Copyright (c) 2017 Jonathan Liu.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/io.h>
10 #include <linux/of_address.h>
11
12 #include "ccu_common.h"
13 #include "ccu_reset.h"
14
15 #include "ccu_div.h"
16 #include "ccu_gate.h"
17 #include "ccu_mp.h"
18 #include "ccu_mult.h"
19 #include "ccu_nk.h"
20 #include "ccu_nkm.h"
21 #include "ccu_nkmp.h"
22 #include "ccu_nm.h"
23 #include "ccu_phase.h"
24 #include "ccu_sdm.h"
25
26 #include "ccu-sun4i-a10.h"
27
28 static struct ccu_nkmp pll_core_clk = {
29 .enable = BIT(31),
30 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
31 .k = _SUNXI_CCU_MULT(4, 2),
32 .m = _SUNXI_CCU_DIV(0, 2),
33 .p = _SUNXI_CCU_DIV(16, 2),
34 .common = {
35 .reg = 0x000,
36 .hw.init = CLK_HW_INIT("pll-core",
37 "hosc",
38 &ccu_nkmp_ops,
39 0),
40 },
41 };
42
43 /*
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45 * the base (2x, 4x and 8x), and one variable divider (the one true
46 * pll audio).
47 *
48 * With sigma-delta modulation for fractional-N on the audio PLL,
49 * we have to use specific dividers. This means the variable divider
50 * can no longer be used, as the audio codec requests the exact clock
51 * rates we support through this mechanism. So we now hard code the
52 * variable divider to 1. This means the clock rates will no longer
53 * match the clock names.
54 */
55 #define SUN4I_PLL_AUDIO_REG 0x008
56
57 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
60 };
61
62 static struct ccu_nm pll_audio_base_clk = {
63 .enable = BIT(31),
64 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
65 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
66 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
67 0x00c, BIT(31)),
68 .common = {
69 .reg = 0x008,
70 .features = CCU_FEATURE_SIGMA_DELTA_MOD,
71 .hw.init = CLK_HW_INIT("pll-audio-base",
72 "hosc",
73 &ccu_nm_ops,
74 0),
75 },
76
77 };
78
79 static struct ccu_mult pll_video0_clk = {
80 .enable = BIT(31),
81 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
82 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
83 270000000, 297000000),
84 .common = {
85 .reg = 0x010,
86 .features = (CCU_FEATURE_FRACTIONAL |
87 CCU_FEATURE_ALL_PREDIV),
88 .prediv = 8,
89 .hw.init = CLK_HW_INIT("pll-video0",
90 "hosc",
91 &ccu_mult_ops,
92 0),
93 },
94 };
95
96 static struct ccu_nkmp pll_ve_sun4i_clk = {
97 .enable = BIT(31),
98 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
99 .k = _SUNXI_CCU_MULT(4, 2),
100 .m = _SUNXI_CCU_DIV(0, 2),
101 .p = _SUNXI_CCU_DIV(16, 2),
102 .common = {
103 .reg = 0x018,
104 .hw.init = CLK_HW_INIT("pll-ve",
105 "hosc",
106 &ccu_nkmp_ops,
107 0),
108 },
109 };
110
111 static struct ccu_nk pll_ve_sun7i_clk = {
112 .enable = BIT(31),
113 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
114 .k = _SUNXI_CCU_MULT(4, 2),
115 .common = {
116 .reg = 0x018,
117 .hw.init = CLK_HW_INIT("pll-ve",
118 "hosc",
119 &ccu_nk_ops,
120 0),
121 },
122 };
123
124 static struct ccu_nk pll_ddr_base_clk = {
125 .enable = BIT(31),
126 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
127 .k = _SUNXI_CCU_MULT(4, 2),
128 .common = {
129 .reg = 0x020,
130 .hw.init = CLK_HW_INIT("pll-ddr-base",
131 "hosc",
132 &ccu_nk_ops,
133 0),
134 },
135 };
136
137 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
138 CLK_IS_CRITICAL);
139
140 static struct ccu_div pll_ddr_other_clk = {
141 .div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
142 .common = {
143 .reg = 0x020,
144 .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
145 &ccu_div_ops,
146 0),
147 },
148 };
149
150 static struct ccu_nk pll_periph_base_clk = {
151 .enable = BIT(31),
152 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
153 .k = _SUNXI_CCU_MULT(4, 2),
154 .common = {
155 .reg = 0x028,
156 .hw.init = CLK_HW_INIT("pll-periph-base",
157 "hosc",
158 &ccu_nk_ops,
159 0),
160 },
161 };
162
163 static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph",
164 &pll_periph_base_clk.common.hw,
165 2, 1, CLK_SET_RATE_PARENT);
166
167 /* Not documented on A10 */
168 static struct ccu_div pll_periph_sata_clk = {
169 .enable = BIT(14),
170 .div = _SUNXI_CCU_DIV(0, 2),
171 .fixed_post_div = 6,
172 .common = {
173 .reg = 0x028,
174 .features = CCU_FEATURE_FIXED_POSTDIV,
175 .hw.init = CLK_HW_INIT("pll-periph-sata",
176 "pll-periph-base",
177 &ccu_div_ops, 0),
178 },
179 };
180
181 static struct ccu_mult pll_video1_clk = {
182 .enable = BIT(31),
183 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
184 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
185 270000000, 297000000),
186 .common = {
187 .reg = 0x030,
188 .features = (CCU_FEATURE_FRACTIONAL |
189 CCU_FEATURE_ALL_PREDIV),
190 .prediv = 8,
191 .hw.init = CLK_HW_INIT("pll-video1",
192 "hosc",
193 &ccu_mult_ops,
194 0),
195 },
196 };
197
198 /* Not present on A10 */
199 static struct ccu_nk pll_gpu_clk = {
200 .enable = BIT(31),
201 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
202 .k = _SUNXI_CCU_MULT(4, 2),
203 .common = {
204 .reg = 0x040,
205 .hw.init = CLK_HW_INIT("pll-gpu",
206 "hosc",
207 &ccu_nk_ops,
208 0),
209 },
210 };
211
212 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
213
214 static const char *const cpu_parents[] = { "osc32k", "hosc",
215 "pll-core", "pll-periph" };
216 static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
217 { .index = 3, .div = 3, },
218 };
219
220 #define SUN4I_AHB_REG 0x054
221 static struct ccu_mux cpu_clk = {
222 .mux = {
223 .shift = 16,
224 .width = 2,
225 .fixed_predivs = cpu_predivs,
226 .n_predivs = ARRAY_SIZE(cpu_predivs),
227 },
228 .common = {
229 .reg = 0x054,
230 .features = CCU_FEATURE_FIXED_PREDIV,
231 .hw.init = CLK_HW_INIT_PARENTS("cpu",
232 cpu_parents,
233 &ccu_mux_ops,
234 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
235 }
236 };
237
238 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
239
240 static struct ccu_div ahb_sun4i_clk = {
241 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
242 .common = {
243 .reg = 0x054,
244 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
245 },
246 };
247
248 static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
249 "pll-periph" };
250 static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
251 { .index = 1, .div = 2, },
252 { /* Sentinel */ },
253 };
254 static struct ccu_div ahb_sun7i_clk = {
255 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
256 .mux = {
257 .shift = 6,
258 .width = 2,
259 .fixed_predivs = ahb_sun7i_predivs,
260 .n_predivs = ARRAY_SIZE(ahb_sun7i_predivs),
261 },
262
263 .common = {
264 .reg = 0x054,
265 .hw.init = CLK_HW_INIT_PARENTS("ahb",
266 ahb_sun7i_parents,
267 &ccu_div_ops,
268 0),
269 },
270 };
271
272 static struct clk_div_table apb0_div_table[] = {
273 { .val = 0, .div = 2 },
274 { .val = 1, .div = 2 },
275 { .val = 2, .div = 4 },
276 { .val = 3, .div = 8 },
277 { /* Sentinel */ },
278 };
279 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
280 0x054, 8, 2, apb0_div_table, 0);
281
282 static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
283 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
284 0, 5, /* M */
285 16, 2, /* P */
286 24, 2, /* mux */
287 0);
288
289 /* Not present on A20 */
290 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
291 0x05c, BIT(31), 0);
292
293 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
294 0x060, BIT(0), 0);
295 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
296 0x060, BIT(1), 0);
297 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
298 0x060, BIT(2), 0);
299 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
300 0x060, BIT(3), 0);
301 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
302 0x060, BIT(4), 0);
303 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
304 0x060, BIT(5), 0);
305 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
306 0x060, BIT(6), 0);
307 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
308 0x060, BIT(7), 0);
309 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
310 0x060, BIT(8), 0);
311 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
312 0x060, BIT(9), 0);
313 static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
314 0x060, BIT(10), 0);
315 static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",
316 0x060, BIT(11), 0);
317 static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",
318 0x060, BIT(12), 0);
319 static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
320 0x060, BIT(13), 0);
321 static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
322 0x060, BIT(14), CLK_IS_CRITICAL);
323
324 static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",
325 0x060, BIT(16), 0);
326 static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
327 0x060, BIT(17), 0);
328 static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
329 0x060, BIT(18), 0);
330 static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
331 0x060, BIT(20), 0);
332 static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
333 0x060, BIT(21), 0);
334 static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
335 0x060, BIT(22), 0);
336 static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",
337 0x060, BIT(23), 0);
338 static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",
339 0x060, BIT(24), 0);
340 /* Not documented on A20 */
341 static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",
342 0x060, BIT(25), 0);
343 /* Not present on A20 */
344 static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
345 0x060, BIT(26), 0);
346 /* Not present on A10 */
347 static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
348 0x060, BIT(28), 0);
349
350 static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
351 0x064, BIT(0), 0);
352 static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",
353 0x064, BIT(1), 0);
354 static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
355 0x064, BIT(2), 0);
356 static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",
357 0x064, BIT(3), 0);
358 static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",
359 0x064, BIT(4), 0);
360 static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",
361 0x064, BIT(5), 0);
362 static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",
363 0x064, BIT(8), 0);
364 static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",
365 0x064, BIT(9), 0);
366 /* Not present on A10 */
367 static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",
368 0x064, BIT(10), 0);
369 static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",
370 0x064, BIT(11), 0);
371 static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",
372 0x064, BIT(12), 0);
373 static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",
374 0x064, BIT(13), 0);
375 static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",
376 0x064, BIT(14), 0);
377 static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",
378 0x064, BIT(15), 0);
379 /* Not present on A10 */
380 static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",
381 0x064, BIT(17), 0);
382 static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",
383 0x064, BIT(18), 0);
384 static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
385 0x064, BIT(20), 0);
386
387 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
388 0x068, BIT(0), 0);
389 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
390 0x068, BIT(1), 0);
391 static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
392 0x068, BIT(2), 0);
393 static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
394 0x068, BIT(3), 0);
395 /* Not present on A10 */
396 static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
397 0x068, BIT(4), 0);
398 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
399 0x068, BIT(5), 0);
400 static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
401 0x068, BIT(6), 0);
402 static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
403 0x068, BIT(7), 0);
404 /* Not present on A10 */
405 static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
406 0x068, BIT(8), 0);
407 static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
408 0x068, BIT(10), 0);
409
410 static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
411 0x06c, BIT(0), 0);
412 static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
413 0x06c, BIT(1), 0);
414 static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
415 0x06c, BIT(2), 0);
416 /* Not present on A10 */
417 static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",
418 0x06c, BIT(3), 0);
419 static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",
420 0x06c, BIT(4), 0);
421 static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",
422 0x06c, BIT(5), 0);
423 static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",
424 0x06c, BIT(6), 0);
425 static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",
426 0x06c, BIT(7), 0);
427 /* Not present on A10 */
428 static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",
429 0x06c, BIT(15), 0);
430 static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
431 0x06c, BIT(16), 0);
432 static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
433 0x06c, BIT(17), 0);
434 static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
435 0x06c, BIT(18), 0);
436 static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
437 0x06c, BIT(19), 0);
438 static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",
439 0x06c, BIT(20), 0);
440 static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",
441 0x06c, BIT(21), 0);
442 static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",
443 0x06c, BIT(22), 0);
444 static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",
445 0x06c, BIT(23), 0);
446
447 static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
448 "pll-ddr-other" };
449 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
450 0, 4, /* M */
451 16, 2, /* P */
452 24, 2, /* mux */
453 BIT(31), /* gate */
454 0);
455
456 /* Undocumented on A10 */
457 static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
458 0, 4, /* M */
459 16, 2, /* P */
460 24, 2, /* mux */
461 BIT(31), /* gate */
462 0);
463
464 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
465 0, 4, /* M */
466 16, 2, /* P */
467 24, 2, /* mux */
468 BIT(31), /* gate */
469 0);
470
471 /* MMC output and sample clocks are not present on A10 */
472 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
473 0x088, 8, 3, 0);
474 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
475 0x088, 20, 3, 0);
476
477 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
478 0, 4, /* M */
479 16, 2, /* P */
480 24, 2, /* mux */
481 BIT(31), /* gate */
482 0);
483
484 /* MMC output and sample clocks are not present on A10 */
485 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
486 0x08c, 8, 3, 0);
487 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
488 0x08c, 20, 3, 0);
489
490 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
491 0, 4, /* M */
492 16, 2, /* P */
493 24, 2, /* mux */
494 BIT(31), /* gate */
495 0);
496
497 /* MMC output and sample clocks are not present on A10 */
498 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
499 0x090, 8, 3, 0);
500 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
501 0x090, 20, 3, 0);
502
503 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
504 0, 4, /* M */
505 16, 2, /* P */
506 24, 2, /* mux */
507 BIT(31), /* gate */
508 0);
509
510 /* MMC output and sample clocks are not present on A10 */
511 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
512 0x094, 8, 3, 0);
513 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
514 0x094, 20, 3, 0);
515
516 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
517 0, 4, /* M */
518 16, 2, /* P */
519 24, 2, /* mux */
520 BIT(31), /* gate */
521 0);
522
523 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
524 0, 4, /* M */
525 16, 2, /* P */
526 24, 2, /* mux */
527 BIT(31), /* gate */
528 0);
529
530 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
531 0, 4, /* M */
532 16, 2, /* P */
533 24, 2, /* mux */
534 BIT(31), /* gate */
535 0);
536
537 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
538 0, 4, /* M */
539 16, 2, /* P */
540 24, 2, /* mux */
541 BIT(31), /* gate */
542 0);
543
544 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
545 0, 4, /* M */
546 16, 2, /* P */
547 24, 2, /* mux */
548 BIT(31), /* gate */
549 0);
550
551 /* Undocumented on A10 */
552 static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
553 0, 4, /* M */
554 16, 2, /* P */
555 24, 2, /* mux */
556 BIT(31), /* gate */
557 0);
558
559 /* TODO: Check whether A10 actually supports osc32k as 4th parent? */
560 static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
561 "pll-ddr-other" };
562 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
563 0, 4, /* M */
564 16, 2, /* P */
565 24, 2, /* mux */
566 BIT(31), /* gate */
567 0);
568
569 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
570 0, 4, /* M */
571 16, 2, /* P */
572 24, 2, /* mux */
573 BIT(31), /* gate */
574 0);
575 static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
576 "pll-ddr-other", "osc32k" };
577 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
578 0, 4, /* M */
579 16, 2, /* P */
580 24, 2, /* mux */
581 BIT(31), /* gate */
582 0);
583
584 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
585 0, 4, /* M */
586 16, 2, /* P */
587 24, 2, /* mux */
588 BIT(31), /* gate */
589 0);
590
591 static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
592 "pll-audio-2x", "pll-audio" };
593 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
594 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
595
596 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
597 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
598
599 /* Undocumented on A10 */
600 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
601 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
602
603 static const char *const keypad_parents[] = { "hosc", "losc"};
604 static const u8 keypad_table[] = { 0, 2 };
605 static struct ccu_mp keypad_clk = {
606 .enable = BIT(31),
607 .m = _SUNXI_CCU_DIV(0, 5),
608 .p = _SUNXI_CCU_DIV(16, 2),
609 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
610 .common = {
611 .reg = 0x0c4,
612 .hw.init = CLK_HW_INIT_PARENTS("keypad",
613 keypad_parents,
614 &ccu_mp_ops,
615 0),
616 },
617 };
618
619 /*
620 * SATA supports external clock as parent via BIT(24) and is probably an
621 * optional crystal or oscillator that can be connected to the
622 * SATA-CLKM / SATA-CLKP pins.
623 */
624 static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
625 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
626 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
627
628
629 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",
630 0x0cc, BIT(6), 0);
631 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",
632 0x0cc, BIT(7), 0);
633 static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",
634 0x0cc, BIT(8), 0);
635
636 /* TODO: GPS CLK 0x0d0 */
637
638 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
639 0, 4, /* M */
640 16, 2, /* P */
641 24, 2, /* mux */
642 BIT(31), /* gate */
643 0);
644
645 /* Not present on A10 */
646 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
647 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
648
649 /* Not present on A10 */
650 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
651 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
652
653 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
654 0x100, BIT(0), 0);
655 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",
656 0x100, BIT(1), 0);
657 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",
658 0x100, BIT(2), 0);
659 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
660 0x100, BIT(3), 0);
661 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
662 0x100, BIT(4), 0);
663 static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
664 0x100, BIT(5), 0);
665 static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",
666 0x100, BIT(6), 0);
667
668 /* Clock seems to be critical only on sun4i */
669 static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",
670 0x100, BIT(15), CLK_IS_CRITICAL);
671 static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",
672 0x100, BIT(24), 0);
673 static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",
674 0x100, BIT(25), 0);
675 static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",
676 0x100, BIT(26), 0);
677 static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",
678 0x100, BIT(27), 0);
679 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",
680 0x100, BIT(28), 0);
681 static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
682 0x100, BIT(29), 0);
683
684 static const char *const de_parents[] = { "pll-video0", "pll-video1",
685 "pll-ddr-other" };
686 static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
687 0x104, 0, 4, 24, 2, BIT(31), 0);
688
689 static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
690 0x108, 0, 4, 24, 2, BIT(31), 0);
691
692 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
693 0x10c, 0, 4, 24, 2, BIT(31), 0);
694
695 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
696 0x110, 0, 4, 24, 2, BIT(31), 0);
697
698 /* Undocumented on A10 */
699 static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
700 0x114, 0, 4, 24, 2, BIT(31), 0);
701
702 static const char *const disp_parents[] = { "pll-video0", "pll-video1",
703 "pll-video0-2x", "pll-video1-2x" };
704 static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
705 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
706 static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
707 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
708
709 static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
710 "pll-ddr-other", "pll-periph" };
711
712 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
713 csi_sclk_parents,
714 0x120, 0, 4, 24, 2, BIT(31), 0);
715
716 /* TVD clock setup for A10 */
717 static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
718 static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
719 0x128, 24, 1, BIT(31), 0);
720
721 /* TVD clock setup for A20 */
722 static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
723 "tvd-sclk2", tvd_parents,
724 0x128,
725 0, 4, /* M */
726 16, 4, /* P */
727 8, 1, /* mux */
728 BIT(15), /* gate */
729 0);
730
731 static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
732 0x128, 0, 4, BIT(31), 0);
733
734 static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
735 disp_parents,
736 0x12c, 0, 4, 24, 2, BIT(31),
737 CLK_SET_RATE_PARENT);
738
739 static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
740 "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
741 0x12c, 11, 1, BIT(15),
742 CLK_SET_RATE_PARENT);
743
744 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
745 disp_parents,
746 0x130, 0, 4, 24, 2, BIT(31),
747 CLK_SET_RATE_PARENT);
748
749 static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
750 "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
751 0x130, 11, 1, BIT(15),
752 CLK_SET_RATE_PARENT);
753
754 static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
755 "pll-video0-2x", "pll-video1-2x"};
756 static const u8 csi_table[] = { 0, 1, 2, 5, 6};
757 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
758 csi_parents, csi_table,
759 0x134, 0, 5, 24, 3, BIT(31), 0);
760
761 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
762 csi_parents, csi_table,
763 0x138, 0, 5, 24, 3, BIT(31), 0);
764
765 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
766
767 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
768 0x140, BIT(31), CLK_SET_RATE_PARENT);
769
770 static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
771
772 static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
773 static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
774 0x148, 0, 4, 24, 1, BIT(31), 0);
775
776 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
777 0x150, 0, 4, 24, 2, BIT(31),
778 CLK_SET_RATE_PARENT);
779
780 static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
781 "pll-ddr-other",
782 "pll-video1" };
783 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
784 0x154, 0, 4, 24, 2, BIT(31),
785 CLK_SET_RATE_PARENT);
786
787 static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
788 "pll-ddr-other", "pll-video1",
789 "pll-gpu" };
790 static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
791 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
792 gpu_parents_sun7i, gpu_table_sun7i,
793 0x154, 0, 4, 24, 3, BIT(31),
794 CLK_SET_RATE_PARENT);
795
796 static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
797 "pll-ddr-other" };
798 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
799 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
800 0);
801 static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
802 "pll-ddr-other" };
803 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
804 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
805 CLK_IS_CRITICAL);
806
807 static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
808
809 static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
810 static const u8 hdmi1_table[] = { 0, 1};
811 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
812 hdmi1_parents, hdmi1_table,
813 0x17c, 0, 4, 24, 2, BIT(31),
814 CLK_SET_RATE_PARENT);
815
816 static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
817 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
818 { .index = 0, .div = 750, },
819 };
820
821 static struct ccu_mp out_a_clk = {
822 .enable = BIT(31),
823 .m = _SUNXI_CCU_DIV(8, 5),
824 .p = _SUNXI_CCU_DIV(20, 2),
825 .mux = {
826 .shift = 24,
827 .width = 2,
828 .fixed_predivs = clk_out_predivs,
829 .n_predivs = ARRAY_SIZE(clk_out_predivs),
830 },
831 .common = {
832 .reg = 0x1f0,
833 .features = CCU_FEATURE_FIXED_PREDIV,
834 .hw.init = CLK_HW_INIT_PARENTS("out-a",
835 out_parents,
836 &ccu_mp_ops,
837 0),
838 },
839 };
840 static struct ccu_mp out_b_clk = {
841 .enable = BIT(31),
842 .m = _SUNXI_CCU_DIV(8, 5),
843 .p = _SUNXI_CCU_DIV(20, 2),
844 .mux = {
845 .shift = 24,
846 .width = 2,
847 .fixed_predivs = clk_out_predivs,
848 .n_predivs = ARRAY_SIZE(clk_out_predivs),
849 },
850 .common = {
851 .reg = 0x1f4,
852 .features = CCU_FEATURE_FIXED_PREDIV,
853 .hw.init = CLK_HW_INIT_PARENTS("out-b",
854 out_parents,
855 &ccu_mp_ops,
856 0),
857 },
858 };
859
860 static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
861 &hosc_clk.common,
862 &pll_core_clk.common,
863 &pll_audio_base_clk.common,
864 &pll_video0_clk.common,
865 &pll_ve_sun4i_clk.common,
866 &pll_ve_sun7i_clk.common,
867 &pll_ddr_base_clk.common,
868 &pll_ddr_clk.common,
869 &pll_ddr_other_clk.common,
870 &pll_periph_base_clk.common,
871 &pll_periph_sata_clk.common,
872 &pll_video1_clk.common,
873 &pll_gpu_clk.common,
874 &cpu_clk.common,
875 &axi_clk.common,
876 &axi_dram_clk.common,
877 &ahb_sun4i_clk.common,
878 &ahb_sun7i_clk.common,
879 &apb0_clk.common,
880 &apb1_clk.common,
881 &ahb_otg_clk.common,
882 &ahb_ehci0_clk.common,
883 &ahb_ohci0_clk.common,
884 &ahb_ehci1_clk.common,
885 &ahb_ohci1_clk.common,
886 &ahb_ss_clk.common,
887 &ahb_dma_clk.common,
888 &ahb_bist_clk.common,
889 &ahb_mmc0_clk.common,
890 &ahb_mmc1_clk.common,
891 &ahb_mmc2_clk.common,
892 &ahb_mmc3_clk.common,
893 &ahb_ms_clk.common,
894 &ahb_nand_clk.common,
895 &ahb_sdram_clk.common,
896 &ahb_ace_clk.common,
897 &ahb_emac_clk.common,
898 &ahb_ts_clk.common,
899 &ahb_spi0_clk.common,
900 &ahb_spi1_clk.common,
901 &ahb_spi2_clk.common,
902 &ahb_spi3_clk.common,
903 &ahb_pata_clk.common,
904 &ahb_sata_clk.common,
905 &ahb_gps_clk.common,
906 &ahb_hstimer_clk.common,
907 &ahb_ve_clk.common,
908 &ahb_tvd_clk.common,
909 &ahb_tve0_clk.common,
910 &ahb_tve1_clk.common,
911 &ahb_lcd0_clk.common,
912 &ahb_lcd1_clk.common,
913 &ahb_csi0_clk.common,
914 &ahb_csi1_clk.common,
915 &ahb_hdmi1_clk.common,
916 &ahb_hdmi0_clk.common,
917 &ahb_de_be0_clk.common,
918 &ahb_de_be1_clk.common,
919 &ahb_de_fe0_clk.common,
920 &ahb_de_fe1_clk.common,
921 &ahb_gmac_clk.common,
922 &ahb_mp_clk.common,
923 &ahb_gpu_clk.common,
924 &apb0_codec_clk.common,
925 &apb0_spdif_clk.common,
926 &apb0_ac97_clk.common,
927 &apb0_i2s0_clk.common,
928 &apb0_i2s1_clk.common,
929 &apb0_pio_clk.common,
930 &apb0_ir0_clk.common,
931 &apb0_ir1_clk.common,
932 &apb0_i2s2_clk.common,
933 &apb0_keypad_clk.common,
934 &apb1_i2c0_clk.common,
935 &apb1_i2c1_clk.common,
936 &apb1_i2c2_clk.common,
937 &apb1_i2c3_clk.common,
938 &apb1_can_clk.common,
939 &apb1_scr_clk.common,
940 &apb1_ps20_clk.common,
941 &apb1_ps21_clk.common,
942 &apb1_i2c4_clk.common,
943 &apb1_uart0_clk.common,
944 &apb1_uart1_clk.common,
945 &apb1_uart2_clk.common,
946 &apb1_uart3_clk.common,
947 &apb1_uart4_clk.common,
948 &apb1_uart5_clk.common,
949 &apb1_uart6_clk.common,
950 &apb1_uart7_clk.common,
951 &nand_clk.common,
952 &ms_clk.common,
953 &mmc0_clk.common,
954 &mmc0_output_clk.common,
955 &mmc0_sample_clk.common,
956 &mmc1_clk.common,
957 &mmc1_output_clk.common,
958 &mmc1_sample_clk.common,
959 &mmc2_clk.common,
960 &mmc2_output_clk.common,
961 &mmc2_sample_clk.common,
962 &mmc3_clk.common,
963 &mmc3_output_clk.common,
964 &mmc3_sample_clk.common,
965 &ts_clk.common,
966 &ss_clk.common,
967 &spi0_clk.common,
968 &spi1_clk.common,
969 &spi2_clk.common,
970 &pata_clk.common,
971 &ir0_sun4i_clk.common,
972 &ir1_sun4i_clk.common,
973 &ir0_sun7i_clk.common,
974 &ir1_sun7i_clk.common,
975 &i2s0_clk.common,
976 &ac97_clk.common,
977 &spdif_clk.common,
978 &keypad_clk.common,
979 &sata_clk.common,
980 &usb_ohci0_clk.common,
981 &usb_ohci1_clk.common,
982 &usb_phy_clk.common,
983 &spi3_clk.common,
984 &i2s1_clk.common,
985 &i2s2_clk.common,
986 &dram_ve_clk.common,
987 &dram_csi0_clk.common,
988 &dram_csi1_clk.common,
989 &dram_ts_clk.common,
990 &dram_tvd_clk.common,
991 &dram_tve0_clk.common,
992 &dram_tve1_clk.common,
993 &dram_out_clk.common,
994 &dram_de_fe1_clk.common,
995 &dram_de_fe0_clk.common,
996 &dram_de_be0_clk.common,
997 &dram_de_be1_clk.common,
998 &dram_mp_clk.common,
999 &dram_ace_clk.common,
1000 &de_be0_clk.common,
1001 &de_be1_clk.common,
1002 &de_fe0_clk.common,
1003 &de_fe1_clk.common,
1004 &de_mp_clk.common,
1005 &tcon0_ch0_clk.common,
1006 &tcon1_ch0_clk.common,
1007 &csi_sclk_clk.common,
1008 &tvd_sun4i_clk.common,
1009 &tvd_sclk1_sun7i_clk.common,
1010 &tvd_sclk2_sun7i_clk.common,
1011 &tcon0_ch1_sclk2_clk.common,
1012 &tcon0_ch1_clk.common,
1013 &tcon1_ch1_sclk2_clk.common,
1014 &tcon1_ch1_clk.common,
1015 &csi0_clk.common,
1016 &csi1_clk.common,
1017 &ve_clk.common,
1018 &codec_clk.common,
1019 &avs_clk.common,
1020 &ace_clk.common,
1021 &hdmi_clk.common,
1022 &gpu_sun4i_clk.common,
1023 &gpu_sun7i_clk.common,
1024 &mbus_sun4i_clk.common,
1025 &mbus_sun7i_clk.common,
1026 &hdmi1_slow_clk.common,
1027 &hdmi1_clk.common,
1028 &out_a_clk.common,
1029 &out_b_clk.common
1030 };
1031
1032 static const struct clk_hw *clk_parent_pll_audio[] = {
1033 &pll_audio_base_clk.common.hw
1034 };
1035
1036 /* Post-divider for pll-audio is hardcoded to 1 */
1037 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
1038 clk_parent_pll_audio,
1039 1, 1, CLK_SET_RATE_PARENT);
1040 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
1041 clk_parent_pll_audio,
1042 2, 1, CLK_SET_RATE_PARENT);
1043 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
1044 clk_parent_pll_audio,
1045 1, 1, CLK_SET_RATE_PARENT);
1046 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
1047 clk_parent_pll_audio,
1048 1, 2, CLK_SET_RATE_PARENT);
1049 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
1050 &pll_video0_clk.common.hw,
1051 1, 2, CLK_SET_RATE_PARENT);
1052 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
1053 &pll_video1_clk.common.hw,
1054 1, 2, CLK_SET_RATE_PARENT);
1055
1056
1057 static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
1058 .hws = {
1059 [CLK_HOSC] = &hosc_clk.common.hw,
1060 [CLK_PLL_CORE] = &pll_core_clk.common.hw,
1061 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
1062 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
1063 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
1064 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
1065 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
1066 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
1067 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1068 [CLK_PLL_VE] = &pll_ve_sun4i_clk.common.hw,
1069 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
1070 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
1071 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
1072 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
1073 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
1074 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
1075 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
1076 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1077 [CLK_CPU] = &cpu_clk.common.hw,
1078 [CLK_AXI] = &axi_clk.common.hw,
1079 [CLK_AXI_DRAM] = &axi_dram_clk.common.hw,
1080 [CLK_AHB] = &ahb_sun4i_clk.common.hw,
1081 [CLK_APB0] = &apb0_clk.common.hw,
1082 [CLK_APB1] = &apb1_clk.common.hw,
1083 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
1084 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
1085 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
1086 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
1087 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
1088 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
1089 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
1090 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
1091 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
1092 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
1093 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
1094 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
1095 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
1096 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
1097 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
1098 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
1099 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
1100 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
1101 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
1102 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
1103 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
1104 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
1105 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
1106 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
1107 [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
1108 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
1109 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
1110 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
1111 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
1112 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
1113 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
1114 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
1115 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
1116 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
1117 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
1118 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
1119 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
1120 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
1121 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
1122 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
1123 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
1124 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
1125 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
1126 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
1127 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
1128 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
1129 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
1130 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
1131 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
1132 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
1133 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
1134 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
1135 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
1136 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
1137 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
1138 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
1139 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
1140 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
1141 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
1142 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
1143 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
1144 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
1145 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
1146 [CLK_NAND] = &nand_clk.common.hw,
1147 [CLK_MS] = &ms_clk.common.hw,
1148 [CLK_MMC0] = &mmc0_clk.common.hw,
1149 [CLK_MMC1] = &mmc1_clk.common.hw,
1150 [CLK_MMC2] = &mmc2_clk.common.hw,
1151 [CLK_MMC3] = &mmc3_clk.common.hw,
1152 [CLK_TS] = &ts_clk.common.hw,
1153 [CLK_SS] = &ss_clk.common.hw,
1154 [CLK_SPI0] = &spi0_clk.common.hw,
1155 [CLK_SPI1] = &spi1_clk.common.hw,
1156 [CLK_SPI2] = &spi2_clk.common.hw,
1157 [CLK_PATA] = &pata_clk.common.hw,
1158 [CLK_IR0] = &ir0_sun4i_clk.common.hw,
1159 [CLK_IR1] = &ir1_sun4i_clk.common.hw,
1160 [CLK_I2S0] = &i2s0_clk.common.hw,
1161 [CLK_AC97] = &ac97_clk.common.hw,
1162 [CLK_SPDIF] = &spdif_clk.common.hw,
1163 [CLK_KEYPAD] = &keypad_clk.common.hw,
1164 [CLK_SATA] = &sata_clk.common.hw,
1165 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1166 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1167 [CLK_USB_PHY] = &usb_phy_clk.common.hw,
1168 /* CLK_GPS is unimplemented */
1169 [CLK_SPI3] = &spi3_clk.common.hw,
1170 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1171 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1172 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1173 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1174 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1175 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
1176 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
1177 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
1178 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
1179 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
1180 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
1181 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
1182 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1183 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
1184 [CLK_DE_BE0] = &de_be0_clk.common.hw,
1185 [CLK_DE_BE1] = &de_be1_clk.common.hw,
1186 [CLK_DE_FE0] = &de_fe0_clk.common.hw,
1187 [CLK_DE_FE1] = &de_fe1_clk.common.hw,
1188 [CLK_DE_MP] = &de_mp_clk.common.hw,
1189 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
1190 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
1191 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1192 [CLK_TVD] = &tvd_sun4i_clk.common.hw,
1193 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
1194 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
1195 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
1196 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
1197 [CLK_CSI0] = &csi0_clk.common.hw,
1198 [CLK_CSI1] = &csi1_clk.common.hw,
1199 [CLK_VE] = &ve_clk.common.hw,
1200 [CLK_CODEC] = &codec_clk.common.hw,
1201 [CLK_AVS] = &avs_clk.common.hw,
1202 [CLK_ACE] = &ace_clk.common.hw,
1203 [CLK_HDMI] = &hdmi_clk.common.hw,
1204 [CLK_GPU] = &gpu_sun7i_clk.common.hw,
1205 [CLK_MBUS] = &mbus_sun4i_clk.common.hw,
1206 },
1207 .num = CLK_NUMBER_SUN4I,
1208 };
1209 static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
1210 .hws = {
1211 [CLK_HOSC] = &hosc_clk.common.hw,
1212 [CLK_PLL_CORE] = &pll_core_clk.common.hw,
1213 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
1214 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
1215 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
1216 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
1217 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
1218 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
1219 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1220 [CLK_PLL_VE] = &pll_ve_sun7i_clk.common.hw,
1221 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
1222 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
1223 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
1224 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
1225 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
1226 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
1227 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
1228 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1229 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
1230 [CLK_CPU] = &cpu_clk.common.hw,
1231 [CLK_AXI] = &axi_clk.common.hw,
1232 [CLK_AHB] = &ahb_sun7i_clk.common.hw,
1233 [CLK_APB0] = &apb0_clk.common.hw,
1234 [CLK_APB1] = &apb1_clk.common.hw,
1235 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
1236 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
1237 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
1238 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
1239 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
1240 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
1241 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
1242 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
1243 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
1244 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
1245 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
1246 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
1247 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
1248 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
1249 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
1250 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
1251 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
1252 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
1253 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
1254 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
1255 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
1256 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
1257 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
1258 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
1259 [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
1260 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
1261 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
1262 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
1263 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
1264 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
1265 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
1266 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
1267 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
1268 [CLK_AHB_HDMI1] = &ahb_hdmi1_clk.common.hw,
1269 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
1270 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
1271 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
1272 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
1273 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
1274 [CLK_AHB_GMAC] = &ahb_gmac_clk.common.hw,
1275 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
1276 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
1277 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
1278 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
1279 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
1280 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
1281 [CLK_APB0_I2S1] = &apb0_i2s1_clk.common.hw,
1282 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
1283 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
1284 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
1285 [CLK_APB0_I2S2] = &apb0_i2s2_clk.common.hw,
1286 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
1287 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
1288 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
1289 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
1290 [CLK_APB1_I2C3] = &apb1_i2c3_clk.common.hw,
1291 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
1292 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
1293 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
1294 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
1295 [CLK_APB1_I2C4] = &apb1_i2c4_clk.common.hw,
1296 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
1297 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
1298 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
1299 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
1300 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
1301 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
1302 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
1303 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
1304 [CLK_NAND] = &nand_clk.common.hw,
1305 [CLK_MS] = &ms_clk.common.hw,
1306 [CLK_MMC0] = &mmc0_clk.common.hw,
1307 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
1308 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
1309 [CLK_MMC1] = &mmc1_clk.common.hw,
1310 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
1311 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
1312 [CLK_MMC2] = &mmc2_clk.common.hw,
1313 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
1314 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
1315 [CLK_MMC3] = &mmc3_clk.common.hw,
1316 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
1317 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
1318 [CLK_TS] = &ts_clk.common.hw,
1319 [CLK_SS] = &ss_clk.common.hw,
1320 [CLK_SPI0] = &spi0_clk.common.hw,
1321 [CLK_SPI1] = &spi1_clk.common.hw,
1322 [CLK_SPI2] = &spi2_clk.common.hw,
1323 [CLK_PATA] = &pata_clk.common.hw,
1324 [CLK_IR0] = &ir0_sun7i_clk.common.hw,
1325 [CLK_IR1] = &ir1_sun7i_clk.common.hw,
1326 [CLK_I2S0] = &i2s0_clk.common.hw,
1327 [CLK_AC97] = &ac97_clk.common.hw,
1328 [CLK_SPDIF] = &spdif_clk.common.hw,
1329 [CLK_KEYPAD] = &keypad_clk.common.hw,
1330 [CLK_SATA] = &sata_clk.common.hw,
1331 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1332 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1333 [CLK_USB_PHY] = &usb_phy_clk.common.hw,
1334 /* CLK_GPS is unimplemented */
1335 [CLK_SPI3] = &spi3_clk.common.hw,
1336 [CLK_I2S1] = &i2s1_clk.common.hw,
1337 [CLK_I2S2] = &i2s2_clk.common.hw,
1338 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1339 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1340 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1341 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1342 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1343 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
1344 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
1345 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
1346 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
1347 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
1348 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
1349 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
1350 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1351 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
1352 [CLK_DE_BE0] = &de_be0_clk.common.hw,
1353 [CLK_DE_BE1] = &de_be1_clk.common.hw,
1354 [CLK_DE_FE0] = &de_fe0_clk.common.hw,
1355 [CLK_DE_FE1] = &de_fe1_clk.common.hw,
1356 [CLK_DE_MP] = &de_mp_clk.common.hw,
1357 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
1358 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
1359 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1360 [CLK_TVD_SCLK2] = &tvd_sclk2_sun7i_clk.common.hw,
1361 [CLK_TVD] = &tvd_sclk1_sun7i_clk.common.hw,
1362 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
1363 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
1364 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
1365 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
1366 [CLK_CSI0] = &csi0_clk.common.hw,
1367 [CLK_CSI1] = &csi1_clk.common.hw,
1368 [CLK_VE] = &ve_clk.common.hw,
1369 [CLK_CODEC] = &codec_clk.common.hw,
1370 [CLK_AVS] = &avs_clk.common.hw,
1371 [CLK_ACE] = &ace_clk.common.hw,
1372 [CLK_HDMI] = &hdmi_clk.common.hw,
1373 [CLK_GPU] = &gpu_sun7i_clk.common.hw,
1374 [CLK_MBUS] = &mbus_sun7i_clk.common.hw,
1375 [CLK_HDMI1_SLOW] = &hdmi1_slow_clk.common.hw,
1376 [CLK_HDMI1] = &hdmi1_clk.common.hw,
1377 [CLK_OUT_A] = &out_a_clk.common.hw,
1378 [CLK_OUT_B] = &out_b_clk.common.hw,
1379 },
1380 .num = CLK_NUMBER_SUN7I,
1381 };
1382
1383 static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
1384 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1385 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1386 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1387 [RST_GPS] = { 0x0d0, BIT(0) },
1388 [RST_DE_BE0] = { 0x104, BIT(30) },
1389 [RST_DE_BE1] = { 0x108, BIT(30) },
1390 [RST_DE_FE0] = { 0x10c, BIT(30) },
1391 [RST_DE_FE1] = { 0x110, BIT(30) },
1392 [RST_DE_MP] = { 0x114, BIT(30) },
1393 [RST_TVE0] = { 0x118, BIT(29) },
1394 [RST_TCON0] = { 0x118, BIT(30) },
1395 [RST_TVE1] = { 0x11c, BIT(29) },
1396 [RST_TCON1] = { 0x11c, BIT(30) },
1397 [RST_CSI0] = { 0x134, BIT(30) },
1398 [RST_CSI1] = { 0x138, BIT(30) },
1399 [RST_VE] = { 0x13c, BIT(0) },
1400 [RST_ACE] = { 0x148, BIT(16) },
1401 [RST_LVDS] = { 0x14c, BIT(0) },
1402 [RST_GPU] = { 0x154, BIT(30) },
1403 [RST_HDMI_H] = { 0x170, BIT(0) },
1404 [RST_HDMI_SYS] = { 0x170, BIT(1) },
1405 [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },
1406 };
1407
1408 static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
1409 .ccu_clks = sun4i_sun7i_ccu_clks,
1410 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1411
1412 .hw_clks = &sun4i_a10_hw_clks,
1413
1414 .resets = sunxi_a10_a20_ccu_resets,
1415 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1416 };
1417
1418 static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
1419 .ccu_clks = sun4i_sun7i_ccu_clks,
1420 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1421
1422 .hw_clks = &sun7i_a20_hw_clks,
1423
1424 .resets = sunxi_a10_a20_ccu_resets,
1425 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1426 };
1427
sun4i_ccu_init(struct device_node * node,const struct sunxi_ccu_desc * desc)1428 static void __init sun4i_ccu_init(struct device_node *node,
1429 const struct sunxi_ccu_desc *desc)
1430 {
1431 void __iomem *reg;
1432 u32 val;
1433
1434 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1435 if (IS_ERR(reg)) {
1436 pr_err("%s: Could not map the clock registers\n",
1437 of_node_full_name(node));
1438 return;
1439 }
1440
1441 val = readl(reg + SUN4I_PLL_AUDIO_REG);
1442
1443 /*
1444 * Force VCO and PLL bias current to lowest setting. Higher
1445 * settings interfere with sigma-delta modulation and result
1446 * in audible noise and distortions when using SPDIF or I2S.
1447 */
1448 val &= ~GENMASK(25, 16);
1449
1450 /* Force the PLL-Audio-1x divider to 1 */
1451 val &= ~GENMASK(29, 26);
1452 writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
1453
1454 /*
1455 * Use the peripheral PLL6 as the AHB parent, instead of CPU /
1456 * AXI which have rate changes due to cpufreq.
1457 *
1458 * This is especially a big deal for the HS timer whose parent
1459 * clock is AHB.
1460 *
1461 * NB! These bits are undocumented in A10 manual.
1462 */
1463 val = readl(reg + SUN4I_AHB_REG);
1464 val &= ~GENMASK(7, 6);
1465 writel(val | (2 << 6), reg + SUN4I_AHB_REG);
1466
1467 sunxi_ccu_probe(node, reg, desc);
1468 }
1469
sun4i_a10_ccu_setup(struct device_node * node)1470 static void __init sun4i_a10_ccu_setup(struct device_node *node)
1471 {
1472 sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
1473 }
1474 CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1475 sun4i_a10_ccu_setup);
1476
sun7i_a20_ccu_setup(struct device_node * node)1477 static void __init sun7i_a20_ccu_setup(struct device_node *node)
1478 {
1479 sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
1480 }
1481 CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
1482 sun7i_a20_ccu_setup);
1483
