1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SAMSUNG EXYNOS5250 SoC device tree source 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. 9 * EXYNOS5250 based board files can include this file and provide 10 * values for board specfic bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, 14 * additional nodes can be added to this file. 15 */ 16 17#include <dt-bindings/clock/exynos5250.h> 18#include "exynos5.dtsi" 19#include "exynos4-cpu-thermal.dtsi" 20#include <dt-bindings/clock/exynos-audss-clk.h> 21 22/ { 23 compatible = "samsung,exynos5250", "samsung,exynos5"; 24 25 aliases { 26 spi0 = &spi_0; 27 spi1 = &spi_1; 28 spi2 = &spi_2; 29 gsc0 = &gsc_0; 30 gsc1 = &gsc_1; 31 gsc2 = &gsc_2; 32 gsc3 = &gsc_3; 33 mshc0 = &mmc_0; 34 mshc1 = &mmc_1; 35 mshc2 = &mmc_2; 36 mshc3 = &mmc_3; 37 i2c4 = &i2c_4; 38 i2c5 = &i2c_5; 39 i2c6 = &i2c_6; 40 i2c7 = &i2c_7; 41 i2c8 = &i2c_8; 42 i2c9 = &i2c_9; 43 pinctrl0 = &pinctrl_0; 44 pinctrl1 = &pinctrl_1; 45 pinctrl2 = &pinctrl_2; 46 pinctrl3 = &pinctrl_3; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a15"; 56 reg = <0>; 57 clocks = <&clock CLK_ARM_CLK>; 58 clock-names = "cpu"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 #cooling-cells = <2>; /* min followed by max */ 61 }; 62 cpu1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a15"; 65 reg = <1>; 66 clocks = <&clock CLK_ARM_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 #cooling-cells = <2>; /* min followed by max */ 70 }; 71 }; 72 73 cpu0_opp_table: opp_table0 { 74 compatible = "operating-points-v2"; 75 opp-shared; 76 77 opp-200000000 { 78 opp-hz = /bits/ 64 <200000000>; 79 opp-microvolt = <925000>; 80 clock-latency-ns = <140000>; 81 }; 82 opp-300000000 { 83 opp-hz = /bits/ 64 <300000000>; 84 opp-microvolt = <937500>; 85 clock-latency-ns = <140000>; 86 }; 87 opp-400000000 { 88 opp-hz = /bits/ 64 <400000000>; 89 opp-microvolt = <950000>; 90 clock-latency-ns = <140000>; 91 }; 92 opp-500000000 { 93 opp-hz = /bits/ 64 <500000000>; 94 opp-microvolt = <975000>; 95 clock-latency-ns = <140000>; 96 }; 97 opp-600000000 { 98 opp-hz = /bits/ 64 <600000000>; 99 opp-microvolt = <1000000>; 100 clock-latency-ns = <140000>; 101 }; 102 opp-700000000 { 103 opp-hz = /bits/ 64 <700000000>; 104 opp-microvolt = <1012500>; 105 clock-latency-ns = <140000>; 106 }; 107 opp-800000000 { 108 opp-hz = /bits/ 64 <800000000>; 109 opp-microvolt = <1025000>; 110 clock-latency-ns = <140000>; 111 }; 112 opp-900000000 { 113 opp-hz = /bits/ 64 <900000000>; 114 opp-microvolt = <1050000>; 115 clock-latency-ns = <140000>; 116 }; 117 opp-1000000000 { 118 opp-hz = /bits/ 64 <1000000000>; 119 opp-microvolt = <1075000>; 120 clock-latency-ns = <140000>; 121 opp-suspend; 122 }; 123 opp-1100000000 { 124 opp-hz = /bits/ 64 <1100000000>; 125 opp-microvolt = <1100000>; 126 clock-latency-ns = <140000>; 127 }; 128 opp-1200000000 { 129 opp-hz = /bits/ 64 <1200000000>; 130 opp-microvolt = <1125000>; 131 clock-latency-ns = <140000>; 132 }; 133 opp-1300000000 { 134 opp-hz = /bits/ 64 <1300000000>; 135 opp-microvolt = <1150000>; 136 clock-latency-ns = <140000>; 137 }; 138 opp-1400000000 { 139 opp-hz = /bits/ 64 <1400000000>; 140 opp-microvolt = <1200000>; 141 clock-latency-ns = <140000>; 142 }; 143 opp-1500000000 { 144 opp-hz = /bits/ 64 <1500000000>; 145 opp-microvolt = <1225000>; 146 clock-latency-ns = <140000>; 147 }; 148 opp-1600000000 { 149 opp-hz = /bits/ 64 <1600000000>; 150 opp-microvolt = <1250000>; 151 clock-latency-ns = <140000>; 152 }; 153 opp-1700000000 { 154 opp-hz = /bits/ 64 <1700000000>; 155 opp-microvolt = <1300000>; 156 clock-latency-ns = <140000>; 157 }; 158 }; 159 160 pmu { 161 compatible = "arm,cortex-a15-pmu"; 162 interrupt-parent = <&combiner>; 163 interrupts = <1 2>, <22 4>; 164 }; 165 166 soc: soc { 167 sysram@2020000 { 168 compatible = "mmio-sram"; 169 reg = <0x02020000 0x30000>; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0 0x02020000 0x30000>; 173 174 smp-sysram@0 { 175 compatible = "samsung,exynos4210-sysram"; 176 reg = <0x0 0x1000>; 177 }; 178 179 smp-sysram@2f000 { 180 compatible = "samsung,exynos4210-sysram-ns"; 181 reg = <0x2f000 0x1000>; 182 }; 183 }; 184 185 pd_gsc: power-domain@10044000 { 186 compatible = "samsung,exynos4210-pd"; 187 reg = <0x10044000 0x20>; 188 #power-domain-cells = <0>; 189 label = "GSC"; 190 }; 191 192 pd_mfc: power-domain@10044040 { 193 compatible = "samsung,exynos4210-pd"; 194 reg = <0x10044040 0x20>; 195 #power-domain-cells = <0>; 196 label = "MFC"; 197 }; 198 199 pd_g3d: power-domain@10044060 { 200 compatible = "samsung,exynos4210-pd"; 201 reg = <0x10044060 0x20>; 202 #power-domain-cells = <0>; 203 label = "G3D"; 204 }; 205 206 pd_disp1: power-domain@100440a0 { 207 compatible = "samsung,exynos4210-pd"; 208 reg = <0x100440A0 0x20>; 209 #power-domain-cells = <0>; 210 label = "DISP1"; 211 }; 212 213 pd_mau: power-domain@100440c0 { 214 compatible = "samsung,exynos4210-pd"; 215 reg = <0x100440C0 0x20>; 216 #power-domain-cells = <0>; 217 label = "MAU"; 218 }; 219 220 clock: clock-controller@10010000 { 221 compatible = "samsung,exynos5250-clock"; 222 reg = <0x10010000 0x30000>; 223 #clock-cells = <1>; 224 }; 225 226 clock_audss: audss-clock-controller@3810000 { 227 compatible = "samsung,exynos5250-audss-clock"; 228 reg = <0x03810000 0x0C>; 229 #clock-cells = <1>; 230 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 231 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 232 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 233 power-domains = <&pd_mau>; 234 }; 235 236 mct@101c0000 { 237 compatible = "samsung,exynos4210-mct"; 238 reg = <0x101C0000 0x800>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupt-parent = <&mct_map>; 242 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 243 <4 0>, <5 0>; 244 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 245 clock-names = "fin_pll", "mct"; 246 247 mct_map: mct-map { 248 #interrupt-cells = <2>; 249 #address-cells = <0>; 250 #size-cells = <0>; 251 interrupt-map = <0x0 0 &combiner 23 3>, 252 <0x1 0 &combiner 23 4>, 253 <0x2 0 &combiner 25 2>, 254 <0x3 0 &combiner 25 3>, 255 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, 256 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>; 257 }; 258 }; 259 260 pinctrl_0: pinctrl@11400000 { 261 compatible = "samsung,exynos5250-pinctrl"; 262 reg = <0x11400000 0x1000>; 263 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 264 265 wakup_eint: wakeup-interrupt-controller { 266 compatible = "samsung,exynos4210-wakeup-eint"; 267 interrupt-parent = <&gic>; 268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 269 }; 270 }; 271 272 pinctrl_1: pinctrl@13400000 { 273 compatible = "samsung,exynos5250-pinctrl"; 274 reg = <0x13400000 0x1000>; 275 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 pinctrl_2: pinctrl@10d10000 { 279 compatible = "samsung,exynos5250-pinctrl"; 280 reg = <0x10d10000 0x1000>; 281 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 282 }; 283 284 pinctrl_3: pinctrl@3860000 { 285 compatible = "samsung,exynos5250-pinctrl"; 286 reg = <0x03860000 0x1000>; 287 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 288 power-domains = <&pd_mau>; 289 }; 290 291 pmu_system_controller: system-controller@10040000 { 292 compatible = "samsung,exynos5250-pmu", "syscon"; 293 reg = <0x10040000 0x5000>; 294 clock-names = "clkout16"; 295 clocks = <&clock CLK_FIN_PLL>; 296 #clock-cells = <1>; 297 interrupt-controller; 298 #interrupt-cells = <3>; 299 interrupt-parent = <&gic>; 300 }; 301 302 watchdog@101d0000 { 303 compatible = "samsung,exynos5250-wdt"; 304 reg = <0x101D0000 0x100>; 305 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clock CLK_WDT>; 307 clock-names = "watchdog"; 308 samsung,syscon-phandle = <&pmu_system_controller>; 309 }; 310 311 mfc: codec@11000000 { 312 compatible = "samsung,mfc-v6"; 313 reg = <0x11000000 0x10000>; 314 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 315 power-domains = <&pd_mfc>; 316 clocks = <&clock CLK_MFC>; 317 clock-names = "mfc"; 318 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 319 iommu-names = "left", "right"; 320 }; 321 322 rotator: rotator@11c00000 { 323 compatible = "samsung,exynos5250-rotator"; 324 reg = <0x11C00000 0x64>; 325 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&clock CLK_ROTATOR>; 327 clock-names = "rotator"; 328 iommus = <&sysmmu_rotator>; 329 }; 330 331 mali: gpu@11800000 { 332 compatible = "samsung,exynos5250-mali", "arm,mali-t604"; 333 reg = <0x11800000 0x5000>; 334 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 337 interrupt-names = "job", "mmu", "gpu"; 338 clocks = <&clock CLK_G3D>; 339 clock-names = "core"; 340 operating-points-v2 = <&gpu_opp_table>; 341 power-domains = <&pd_g3d>; 342 status = "disabled"; 343 344 gpu_opp_table: gpu-opp-table { 345 compatible = "operating-points-v2"; 346 347 opp-100000000 { 348 opp-hz = /bits/ 64 <100000000>; 349 opp-microvolt = <925000>; 350 }; 351 opp-160000000 { 352 opp-hz = /bits/ 64 <160000000>; 353 opp-microvolt = <925000>; 354 }; 355 opp-266000000 { 356 opp-hz = /bits/ 64 <266000000>; 357 opp-microvolt = <1025000>; 358 }; 359 opp-350000000 { 360 opp-hz = /bits/ 64 <350000000>; 361 opp-microvolt = <1075000>; 362 }; 363 opp-400000000 { 364 opp-hz = /bits/ 64 <400000000>; 365 opp-microvolt = <1125000>; 366 }; 367 opp-450000000 { 368 opp-hz = /bits/ 64 <450000000>; 369 opp-microvolt = <1150000>; 370 }; 371 opp-533000000 { 372 opp-hz = /bits/ 64 <533000000>; 373 opp-microvolt = <1250000>; 374 }; 375 }; 376 }; 377 378 tmu: tmu@10060000 { 379 compatible = "samsung,exynos5250-tmu"; 380 reg = <0x10060000 0x100>; 381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clock CLK_TMU>; 383 clock-names = "tmu_apbif"; 384 #thermal-sensor-cells = <0>; 385 }; 386 387 sata: sata@122f0000 { 388 compatible = "snps,dwc-ahci"; 389 samsung,sata-freq = <66>; 390 reg = <0x122F0000 0x1ff>; 391 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 393 clock-names = "sata", "sclk_sata"; 394 phys = <&sata_phy>; 395 phy-names = "sata-phy"; 396 ports-implemented = <0x1>; 397 status = "disabled"; 398 }; 399 400 sata_phy: sata-phy@12170000 { 401 compatible = "samsung,exynos5250-sata-phy"; 402 reg = <0x12170000 0x1ff>; 403 clocks = <&clock CLK_SATA_PHYCTRL>; 404 clock-names = "sata_phyctrl"; 405 #phy-cells = <0>; 406 samsung,syscon-phandle = <&pmu_system_controller>; 407 status = "disabled"; 408 }; 409 410 /* i2c_0-3 are defined in exynos5.dtsi */ 411 i2c_4: i2c@12ca0000 { 412 compatible = "samsung,s3c2440-i2c"; 413 reg = <0x12CA0000 0x100>; 414 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clocks = <&clock CLK_I2C4>; 418 clock-names = "i2c"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2c4_bus>; 421 status = "disabled"; 422 }; 423 424 i2c_5: i2c@12cb0000 { 425 compatible = "samsung,s3c2440-i2c"; 426 reg = <0x12CB0000 0x100>; 427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&clock CLK_I2C5>; 431 clock-names = "i2c"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&i2c5_bus>; 434 status = "disabled"; 435 }; 436 437 i2c_6: i2c@12cc0000 { 438 compatible = "samsung,s3c2440-i2c"; 439 reg = <0x12CC0000 0x100>; 440 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 clocks = <&clock CLK_I2C6>; 444 clock-names = "i2c"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&i2c6_bus>; 447 status = "disabled"; 448 }; 449 450 i2c_7: i2c@12cd0000 { 451 compatible = "samsung,s3c2440-i2c"; 452 reg = <0x12CD0000 0x100>; 453 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 clocks = <&clock CLK_I2C7>; 457 clock-names = "i2c"; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&i2c7_bus>; 460 status = "disabled"; 461 }; 462 463 i2c_8: i2c@12ce0000 { 464 compatible = "samsung,s3c2440-hdmiphy-i2c"; 465 reg = <0x12CE0000 0x1000>; 466 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 clocks = <&clock CLK_I2C_HDMI>; 470 clock-names = "i2c"; 471 status = "disabled"; 472 473 hdmiphy: hdmiphy@38 { 474 compatible = "samsung,exynos4212-hdmiphy"; 475 reg = <0x38>; 476 }; 477 }; 478 479 i2c_9: i2c@121d0000 { 480 compatible = "samsung,exynos5-sata-phy-i2c"; 481 reg = <0x121D0000 0x100>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clocks = <&clock CLK_SATA_PHYI2C>; 485 clock-names = "i2c"; 486 status = "disabled"; 487 }; 488 489 spi_0: spi@12d20000 { 490 compatible = "samsung,exynos4210-spi"; 491 status = "disabled"; 492 reg = <0x12d20000 0x100>; 493 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 494 dmas = <&pdma0 5 495 &pdma0 4>; 496 dma-names = "tx", "rx"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 500 clock-names = "spi", "spi_busclk0"; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&spi0_bus>; 503 }; 504 505 spi_1: spi@12d30000 { 506 compatible = "samsung,exynos4210-spi"; 507 status = "disabled"; 508 reg = <0x12d30000 0x100>; 509 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 510 dmas = <&pdma1 5 511 &pdma1 4>; 512 dma-names = "tx", "rx"; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 516 clock-names = "spi", "spi_busclk0"; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&spi1_bus>; 519 }; 520 521 spi_2: spi@12d40000 { 522 compatible = "samsung,exynos4210-spi"; 523 status = "disabled"; 524 reg = <0x12d40000 0x100>; 525 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 526 dmas = <&pdma0 7 527 &pdma0 6>; 528 dma-names = "tx", "rx"; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 532 clock-names = "spi", "spi_busclk0"; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&spi2_bus>; 535 }; 536 537 mmc_0: mmc@12200000 { 538 compatible = "samsung,exynos5250-dw-mshc"; 539 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 reg = <0x12200000 0x1000>; 543 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 544 clock-names = "biu", "ciu"; 545 fifo-depth = <0x80>; 546 status = "disabled"; 547 }; 548 549 mmc_1: mmc@12210000 { 550 compatible = "samsung,exynos5250-dw-mshc"; 551 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 reg = <0x12210000 0x1000>; 555 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 556 clock-names = "biu", "ciu"; 557 fifo-depth = <0x80>; 558 status = "disabled"; 559 }; 560 561 mmc_2: mmc@12220000 { 562 compatible = "samsung,exynos5250-dw-mshc"; 563 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <0x12220000 0x1000>; 567 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 568 clock-names = "biu", "ciu"; 569 fifo-depth = <0x80>; 570 status = "disabled"; 571 }; 572 573 mmc_3: mmc@12230000 { 574 compatible = "samsung,exynos5250-dw-mshc"; 575 reg = <0x12230000 0x1000>; 576 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 580 clock-names = "biu", "ciu"; 581 fifo-depth = <0x80>; 582 status = "disabled"; 583 }; 584 585 i2s0: i2s@3830000 { 586 compatible = "samsung,s5pv210-i2s"; 587 status = "disabled"; 588 reg = <0x03830000 0x100>; 589 dmas = <&pdma0 10 590 &pdma0 9 591 &pdma0 8>; 592 dma-names = "tx", "rx", "tx-sec"; 593 clocks = <&clock_audss EXYNOS_I2S_BUS>, 594 <&clock_audss EXYNOS_I2S_BUS>, 595 <&clock_audss EXYNOS_SCLK_I2S>; 596 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 597 samsung,idma-addr = <0x03000000>; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&i2s0_bus>; 600 power-domains = <&pd_mau>; 601 #clock-cells = <1>; 602 #sound-dai-cells = <1>; 603 }; 604 605 i2s1: i2s@12d60000 { 606 compatible = "samsung,s3c6410-i2s"; 607 status = "disabled"; 608 reg = <0x12D60000 0x100>; 609 dmas = <&pdma1 12 610 &pdma1 11>; 611 dma-names = "tx", "rx"; 612 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 613 clock-names = "iis", "i2s_opclk0"; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&i2s1_bus>; 616 power-domains = <&pd_mau>; 617 #sound-dai-cells = <1>; 618 }; 619 620 i2s2: i2s@12d70000 { 621 compatible = "samsung,s3c6410-i2s"; 622 status = "disabled"; 623 reg = <0x12D70000 0x100>; 624 dmas = <&pdma0 12 625 &pdma0 11>; 626 dma-names = "tx", "rx"; 627 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 628 clock-names = "iis", "i2s_opclk0"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&i2s2_bus>; 631 power-domains = <&pd_mau>; 632 #sound-dai-cells = <1>; 633 }; 634 635 usb_dwc3 { 636 compatible = "samsung,exynos5250-dwusb3"; 637 clocks = <&clock CLK_USB3>; 638 clock-names = "usbdrd30"; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 ranges; 642 643 usbdrd_dwc3: dwc3@12000000 { 644 compatible = "synopsys,dwc3"; 645 reg = <0x12000000 0x10000>; 646 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 647 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 648 phy-names = "usb2-phy", "usb3-phy"; 649 }; 650 }; 651 652 usbdrd_phy: phy@12100000 { 653 compatible = "samsung,exynos5250-usbdrd-phy"; 654 reg = <0x12100000 0x100>; 655 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 656 clock-names = "phy", "ref"; 657 samsung,pmu-syscon = <&pmu_system_controller>; 658 #phy-cells = <1>; 659 }; 660 661 ehci: usb@12110000 { 662 compatible = "samsung,exynos4210-ehci"; 663 reg = <0x12110000 0x100>; 664 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 665 666 clocks = <&clock CLK_USB2>; 667 clock-names = "usbhost"; 668 phys = <&usb2_phy_gen 1>; 669 phy-names = "host"; 670 }; 671 672 ohci: usb@12120000 { 673 compatible = "samsung,exynos4210-ohci"; 674 reg = <0x12120000 0x100>; 675 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 676 677 clocks = <&clock CLK_USB2>; 678 clock-names = "usbhost"; 679 phys = <&usb2_phy_gen 1>; 680 phy-names = "host"; 681 }; 682 683 usb2_phy_gen: phy@12130000 { 684 compatible = "samsung,exynos5250-usb2-phy"; 685 reg = <0x12130000 0x100>; 686 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; 687 clock-names = "phy", "ref"; 688 #phy-cells = <1>; 689 samsung,sysreg-phandle = <&sysreg_system_controller>; 690 samsung,pmureg-phandle = <&pmu_system_controller>; 691 }; 692 693 amba { 694 #address-cells = <1>; 695 #size-cells = <1>; 696 compatible = "simple-bus"; 697 interrupt-parent = <&gic>; 698 ranges; 699 700 pdma0: pdma@121a0000 { 701 compatible = "arm,pl330", "arm,primecell"; 702 reg = <0x121A0000 0x1000>; 703 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clock CLK_PDMA0>; 705 clock-names = "apb_pclk"; 706 #dma-cells = <1>; 707 #dma-channels = <8>; 708 #dma-requests = <32>; 709 }; 710 711 pdma1: pdma@121b0000 { 712 compatible = "arm,pl330", "arm,primecell"; 713 reg = <0x121B0000 0x1000>; 714 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&clock CLK_PDMA1>; 716 clock-names = "apb_pclk"; 717 #dma-cells = <1>; 718 #dma-channels = <8>; 719 #dma-requests = <32>; 720 }; 721 722 mdma0: mdma@10800000 { 723 compatible = "arm,pl330", "arm,primecell"; 724 reg = <0x10800000 0x1000>; 725 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&clock CLK_MDMA0>; 727 clock-names = "apb_pclk"; 728 #dma-cells = <1>; 729 #dma-channels = <8>; 730 #dma-requests = <1>; 731 }; 732 733 mdma1: mdma@11c10000 { 734 compatible = "arm,pl330", "arm,primecell"; 735 reg = <0x11C10000 0x1000>; 736 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&clock CLK_MDMA1>; 738 clock-names = "apb_pclk"; 739 #dma-cells = <1>; 740 #dma-channels = <8>; 741 #dma-requests = <1>; 742 }; 743 }; 744 745 gsc_0: gsc@13e00000 { 746 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 747 reg = <0x13e00000 0x1000>; 748 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 749 power-domains = <&pd_gsc>; 750 clocks = <&clock CLK_GSCL0>; 751 clock-names = "gscl"; 752 iommus = <&sysmmu_gsc0>; 753 }; 754 755 gsc_1: gsc@13e10000 { 756 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 757 reg = <0x13e10000 0x1000>; 758 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 759 power-domains = <&pd_gsc>; 760 clocks = <&clock CLK_GSCL1>; 761 clock-names = "gscl"; 762 iommus = <&sysmmu_gsc1>; 763 }; 764 765 gsc_2: gsc@13e20000 { 766 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 767 reg = <0x13e20000 0x1000>; 768 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 769 power-domains = <&pd_gsc>; 770 clocks = <&clock CLK_GSCL2>; 771 clock-names = "gscl"; 772 iommus = <&sysmmu_gsc2>; 773 }; 774 775 gsc_3: gsc@13e30000 { 776 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 777 reg = <0x13e30000 0x1000>; 778 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 779 power-domains = <&pd_gsc>; 780 clocks = <&clock CLK_GSCL3>; 781 clock-names = "gscl"; 782 iommus = <&sysmmu_gsc3>; 783 }; 784 785 hdmi: hdmi@14530000 { 786 compatible = "samsung,exynos4212-hdmi"; 787 reg = <0x14530000 0x70000>; 788 power-domains = <&pd_disp1>; 789 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 791 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 792 <&clock CLK_MOUT_HDMI>; 793 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 794 "sclk_hdmiphy", "mout_hdmi"; 795 samsung,syscon-phandle = <&pmu_system_controller>; 796 phy = <&hdmiphy>; 797 #sound-dai-cells = <0>; 798 status = "disabled"; 799 }; 800 801 hdmicec: cec@101b0000 { 802 compatible = "samsung,s5p-cec"; 803 reg = <0x101B0000 0x200>; 804 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&clock CLK_HDMI_CEC>; 806 clock-names = "hdmicec"; 807 samsung,syscon-phandle = <&pmu_system_controller>; 808 hdmi-phandle = <&hdmi>; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&hdmi_cec>; 811 status = "disabled"; 812 }; 813 814 mixer: mixer@14450000 { 815 compatible = "samsung,exynos5250-mixer"; 816 reg = <0x14450000 0x10000>; 817 power-domains = <&pd_disp1>; 818 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 820 <&clock CLK_SCLK_HDMI>; 821 clock-names = "mixer", "hdmi", "sclk_hdmi"; 822 iommus = <&sysmmu_tv>; 823 status = "disabled"; 824 }; 825 826 dp_phy: video-phy { 827 compatible = "samsung,exynos5250-dp-video-phy"; 828 samsung,pmu-syscon = <&pmu_system_controller>; 829 #phy-cells = <0>; 830 }; 831 832 mipi_phy: video-phy@10040710 { 833 compatible = "samsung,s5pv210-mipi-video-phy"; 834 reg = <0x10040710 0x100>; 835 #phy-cells = <1>; 836 syscon = <&pmu_system_controller>; 837 }; 838 839 dsi_0: dsi@14500000 { 840 compatible = "samsung,exynos4210-mipi-dsi"; 841 reg = <0x14500000 0x10000>; 842 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 843 samsung,power-domain = <&pd_disp1>; 844 phys = <&mipi_phy 3>; 845 phy-names = "dsim"; 846 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>; 847 clock-names = "bus_clk", "sclk_mipi"; 848 status = "disabled"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 }; 852 853 adc: adc@12d10000 { 854 compatible = "samsung,exynos-adc-v1"; 855 reg = <0x12D10000 0x100>; 856 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&clock CLK_ADC>; 858 clock-names = "adc"; 859 #io-channel-cells = <1>; 860 io-channel-ranges; 861 samsung,syscon-phandle = <&pmu_system_controller>; 862 status = "disabled"; 863 }; 864 865 sysmmu_g2d: sysmmu@10a60000 { 866 compatible = "samsung,exynos-sysmmu"; 867 reg = <0x10A60000 0x1000>; 868 interrupt-parent = <&combiner>; 869 interrupts = <24 5>; 870 clock-names = "sysmmu", "master"; 871 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; 872 #iommu-cells = <0>; 873 }; 874 875 sysmmu_mfc_r: sysmmu@11200000 { 876 compatible = "samsung,exynos-sysmmu"; 877 reg = <0x11200000 0x1000>; 878 interrupt-parent = <&combiner>; 879 interrupts = <6 2>; 880 power-domains = <&pd_mfc>; 881 clock-names = "sysmmu", "master"; 882 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 883 #iommu-cells = <0>; 884 }; 885 886 sysmmu_mfc_l: sysmmu@11210000 { 887 compatible = "samsung,exynos-sysmmu"; 888 reg = <0x11210000 0x1000>; 889 interrupt-parent = <&combiner>; 890 interrupts = <8 5>; 891 power-domains = <&pd_mfc>; 892 clock-names = "sysmmu", "master"; 893 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 894 #iommu-cells = <0>; 895 }; 896 897 sysmmu_rotator: sysmmu@11d40000 { 898 compatible = "samsung,exynos-sysmmu"; 899 reg = <0x11D40000 0x1000>; 900 interrupt-parent = <&combiner>; 901 interrupts = <4 0>; 902 clock-names = "sysmmu", "master"; 903 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 904 #iommu-cells = <0>; 905 }; 906 907 sysmmu_jpeg: sysmmu@11f20000 { 908 compatible = "samsung,exynos-sysmmu"; 909 reg = <0x11F20000 0x1000>; 910 interrupt-parent = <&combiner>; 911 interrupts = <4 2>; 912 power-domains = <&pd_gsc>; 913 clock-names = "sysmmu", "master"; 914 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 915 #iommu-cells = <0>; 916 }; 917 918 sysmmu_fimc_isp: sysmmu@13260000 { 919 compatible = "samsung,exynos-sysmmu"; 920 reg = <0x13260000 0x1000>; 921 interrupt-parent = <&combiner>; 922 interrupts = <10 6>; 923 clock-names = "sysmmu"; 924 clocks = <&clock CLK_SMMU_FIMC_ISP>; 925 #iommu-cells = <0>; 926 }; 927 928 sysmmu_fimc_drc: sysmmu@13270000 { 929 compatible = "samsung,exynos-sysmmu"; 930 reg = <0x13270000 0x1000>; 931 interrupt-parent = <&combiner>; 932 interrupts = <11 6>; 933 clock-names = "sysmmu"; 934 clocks = <&clock CLK_SMMU_FIMC_DRC>; 935 #iommu-cells = <0>; 936 }; 937 938 sysmmu_fimc_fd: sysmmu@132a0000 { 939 compatible = "samsung,exynos-sysmmu"; 940 reg = <0x132A0000 0x1000>; 941 interrupt-parent = <&combiner>; 942 interrupts = <5 0>; 943 clock-names = "sysmmu"; 944 clocks = <&clock CLK_SMMU_FIMC_FD>; 945 #iommu-cells = <0>; 946 }; 947 948 sysmmu_fimc_scc: sysmmu@13280000 { 949 compatible = "samsung,exynos-sysmmu"; 950 reg = <0x13280000 0x1000>; 951 interrupt-parent = <&combiner>; 952 interrupts = <5 2>; 953 clock-names = "sysmmu"; 954 clocks = <&clock CLK_SMMU_FIMC_SCC>; 955 #iommu-cells = <0>; 956 }; 957 958 sysmmu_fimc_scp: sysmmu@13290000 { 959 compatible = "samsung,exynos-sysmmu"; 960 reg = <0x13290000 0x1000>; 961 interrupt-parent = <&combiner>; 962 interrupts = <3 6>; 963 clock-names = "sysmmu"; 964 clocks = <&clock CLK_SMMU_FIMC_SCP>; 965 #iommu-cells = <0>; 966 }; 967 968 sysmmu_fimc_mcuctl: sysmmu@132b0000 { 969 compatible = "samsung,exynos-sysmmu"; 970 reg = <0x132B0000 0x1000>; 971 interrupt-parent = <&combiner>; 972 interrupts = <5 4>; 973 clock-names = "sysmmu"; 974 clocks = <&clock CLK_SMMU_FIMC_MCU>; 975 #iommu-cells = <0>; 976 }; 977 978 sysmmu_fimc_odc: sysmmu@132c0000 { 979 compatible = "samsung,exynos-sysmmu"; 980 reg = <0x132C0000 0x1000>; 981 interrupt-parent = <&combiner>; 982 interrupts = <11 0>; 983 clock-names = "sysmmu"; 984 clocks = <&clock CLK_SMMU_FIMC_ODC>; 985 #iommu-cells = <0>; 986 }; 987 988 sysmmu_fimc_dis0: sysmmu@132d0000 { 989 compatible = "samsung,exynos-sysmmu"; 990 reg = <0x132D0000 0x1000>; 991 interrupt-parent = <&combiner>; 992 interrupts = <10 4>; 993 clock-names = "sysmmu"; 994 clocks = <&clock CLK_SMMU_FIMC_DIS0>; 995 #iommu-cells = <0>; 996 }; 997 998 sysmmu_fimc_dis1: sysmmu@132e0000 { 999 compatible = "samsung,exynos-sysmmu"; 1000 reg = <0x132E0000 0x1000>; 1001 interrupt-parent = <&combiner>; 1002 interrupts = <9 4>; 1003 clock-names = "sysmmu"; 1004 clocks = <&clock CLK_SMMU_FIMC_DIS1>; 1005 #iommu-cells = <0>; 1006 }; 1007 1008 sysmmu_fimc_3dnr: sysmmu@132f0000 { 1009 compatible = "samsung,exynos-sysmmu"; 1010 reg = <0x132F0000 0x1000>; 1011 interrupt-parent = <&combiner>; 1012 interrupts = <5 6>; 1013 clock-names = "sysmmu"; 1014 clocks = <&clock CLK_SMMU_FIMC_3DNR>; 1015 #iommu-cells = <0>; 1016 }; 1017 1018 sysmmu_fimc_lite0: sysmmu@13c40000 { 1019 compatible = "samsung,exynos-sysmmu"; 1020 reg = <0x13C40000 0x1000>; 1021 interrupt-parent = <&combiner>; 1022 interrupts = <3 4>; 1023 power-domains = <&pd_gsc>; 1024 clock-names = "sysmmu", "master"; 1025 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; 1026 #iommu-cells = <0>; 1027 }; 1028 1029 sysmmu_fimc_lite1: sysmmu@13c50000 { 1030 compatible = "samsung,exynos-sysmmu"; 1031 reg = <0x13C50000 0x1000>; 1032 interrupt-parent = <&combiner>; 1033 interrupts = <24 1>; 1034 power-domains = <&pd_gsc>; 1035 clock-names = "sysmmu", "master"; 1036 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; 1037 #iommu-cells = <0>; 1038 }; 1039 1040 sysmmu_gsc0: sysmmu@13e80000 { 1041 compatible = "samsung,exynos-sysmmu"; 1042 reg = <0x13E80000 0x1000>; 1043 interrupt-parent = <&combiner>; 1044 interrupts = <2 0>; 1045 power-domains = <&pd_gsc>; 1046 clock-names = "sysmmu", "master"; 1047 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 1048 #iommu-cells = <0>; 1049 }; 1050 1051 sysmmu_gsc1: sysmmu@13e90000 { 1052 compatible = "samsung,exynos-sysmmu"; 1053 reg = <0x13E90000 0x1000>; 1054 interrupt-parent = <&combiner>; 1055 interrupts = <2 2>; 1056 power-domains = <&pd_gsc>; 1057 clock-names = "sysmmu", "master"; 1058 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 1059 #iommu-cells = <0>; 1060 }; 1061 1062 sysmmu_gsc2: sysmmu@13ea0000 { 1063 compatible = "samsung,exynos-sysmmu"; 1064 reg = <0x13EA0000 0x1000>; 1065 interrupt-parent = <&combiner>; 1066 interrupts = <2 4>; 1067 power-domains = <&pd_gsc>; 1068 clock-names = "sysmmu", "master"; 1069 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; 1070 #iommu-cells = <0>; 1071 }; 1072 1073 sysmmu_gsc3: sysmmu@13eb0000 { 1074 compatible = "samsung,exynos-sysmmu"; 1075 reg = <0x13EB0000 0x1000>; 1076 interrupt-parent = <&combiner>; 1077 interrupts = <2 6>; 1078 power-domains = <&pd_gsc>; 1079 clock-names = "sysmmu", "master"; 1080 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; 1081 #iommu-cells = <0>; 1082 }; 1083 1084 sysmmu_fimd1: sysmmu@14640000 { 1085 compatible = "samsung,exynos-sysmmu"; 1086 reg = <0x14640000 0x1000>; 1087 interrupt-parent = <&combiner>; 1088 interrupts = <3 2>; 1089 power-domains = <&pd_disp1>; 1090 clock-names = "sysmmu", "master"; 1091 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 1092 #iommu-cells = <0>; 1093 }; 1094 1095 sysmmu_tv: sysmmu@14650000 { 1096 compatible = "samsung,exynos-sysmmu"; 1097 reg = <0x14650000 0x1000>; 1098 interrupt-parent = <&combiner>; 1099 interrupts = <7 4>; 1100 power-domains = <&pd_disp1>; 1101 clock-names = "sysmmu", "master"; 1102 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 1103 #iommu-cells = <0>; 1104 }; 1105 }; 1106 1107 thermal-zones { 1108 cpu_thermal: cpu-thermal { 1109 polling-delay-passive = <0>; 1110 polling-delay = <0>; 1111 thermal-sensors = <&tmu 0>; 1112 1113 cooling-maps { 1114 map0 { 1115 /* Corresponds to 800MHz at freq_table */ 1116 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; 1117 }; 1118 map1 { 1119 /* Corresponds to 200MHz at freq_table */ 1120 cooling-device = <&cpu0 15 15>, 1121 <&cpu1 15 15>; 1122 }; 1123 }; 1124 }; 1125 }; 1126 1127 timer { 1128 compatible = "arm,armv7-timer"; 1129 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1130 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1131 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1132 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1133 /* 1134 * Unfortunately we need this since some versions 1135 * of U-Boot on Exynos don't set the CNTFRQ register, 1136 * so we need the value from DT. 1137 */ 1138 clock-frequency = <24000000>; 1139 }; 1140}; 1141 1142&dp { 1143 power-domains = <&pd_disp1>; 1144 clocks = <&clock CLK_DP>; 1145 clock-names = "dp"; 1146 phys = <&dp_phy>; 1147 phy-names = "dp"; 1148}; 1149 1150&fimd { 1151 power-domains = <&pd_disp1>; 1152 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1153 clock-names = "sclk_fimd", "fimd"; 1154 iommus = <&sysmmu_fimd1>; 1155}; 1156 1157&g2d { 1158 iommus = <&sysmmu_g2d>; 1159 clocks = <&clock CLK_G2D>; 1160 clock-names = "fimg2d"; 1161 status = "okay"; 1162}; 1163 1164&i2c_0 { 1165 clocks = <&clock CLK_I2C0>; 1166 clock-names = "i2c"; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&i2c0_bus>; 1169}; 1170 1171&i2c_1 { 1172 clocks = <&clock CLK_I2C1>; 1173 clock-names = "i2c"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&i2c1_bus>; 1176}; 1177 1178&i2c_2 { 1179 clocks = <&clock CLK_I2C2>; 1180 clock-names = "i2c"; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&i2c2_bus>; 1183}; 1184 1185&i2c_3 { 1186 clocks = <&clock CLK_I2C3>; 1187 clock-names = "i2c"; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&i2c3_bus>; 1190}; 1191 1192&prng { 1193 clocks = <&clock CLK_SSS>; 1194 clock-names = "secss"; 1195}; 1196 1197&pwm { 1198 clocks = <&clock CLK_PWM>; 1199 clock-names = "timers"; 1200}; 1201 1202&rtc { 1203 clocks = <&clock CLK_RTC>; 1204 clock-names = "rtc"; 1205 interrupt-parent = <&pmu_system_controller>; 1206 status = "disabled"; 1207}; 1208 1209&serial_0 { 1210 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1211 clock-names = "uart", "clk_uart_baud0"; 1212 dmas = <&pdma0 13>, <&pdma0 14>; 1213 dma-names = "rx", "tx"; 1214}; 1215 1216&serial_1 { 1217 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1218 clock-names = "uart", "clk_uart_baud0"; 1219 dmas = <&pdma1 15>, <&pdma1 16>; 1220 dma-names = "rx", "tx"; 1221}; 1222 1223&serial_2 { 1224 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1225 clock-names = "uart", "clk_uart_baud0"; 1226 dmas = <&pdma0 15>, <&pdma0 16>; 1227 dma-names = "rx", "tx"; 1228}; 1229 1230&serial_3 { 1231 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1232 clock-names = "uart", "clk_uart_baud0"; 1233 dmas = <&pdma1 17>, <&pdma1 18>; 1234 dma-names = "rx", "tx"; 1235}; 1236 1237&sss { 1238 clocks = <&clock CLK_SSS>; 1239 clock-names = "secss"; 1240}; 1241 1242&trng { 1243 clocks = <&clock CLK_SSS>; 1244 clock-names = "secss"; 1245}; 1246 1247#include "exynos5250-pinctrl.dtsi" 1248#include "exynos-syscon-restart.dtsi" 1249
