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Searched refs:port_clock (Results 1 – 25 of 25) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_ddi_buf_trans.c1176 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1205 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1230 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1257 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1286 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1308 if (crtc_state->port_clock > 540000) { in tgl_get_combo_buf_trans_edp()
1340 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1356 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1387 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1401 if (crtc_state->port_clock > 540000) { in rkl_get_combo_buf_trans_edp()
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Dintel_dp_link_training.c475 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, in intel_dp_prepare_link_train()
627 } else if (crtc_state->port_clock == 810000) { in intel_dp_training_pattern()
645 } else if (crtc_state->port_clock >= 540000) { in intel_dp_training_pattern()
804 crtc_state->port_clock, crtc_state->lane_count, in intel_dp_link_train_phy()
820 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
Dintel_ddi.c216 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
251 static u32 ddi_buf_phy_link_rate(int port_clock) in ddi_buf_phy_link_rate() argument
253 switch (port_clock) { in ddi_buf_phy_link_rate()
271 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
289 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
322 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
325 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
328 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
330 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
1098 rate = crtc_state->port_clock; in icl_combo_phy_ddi_vswing_sequence()
[all …]
Dg4x_dp.c93 if (pipe_config->port_clock == divisor[i].clock) { in g4x_dp_set_clock()
112 pipe_config->port_clock, in intel_dp_prepare()
219 pipe_config->port_clock); in ilk_edp_pll_on()
223 if (pipe_config->port_clock == 162000) in ilk_edp_pll_on()
390 pipe_config->port_clock = 162000; in intel_dp_get_config()
392 pipe_config->port_clock = 270000; in intel_dp_get_config()
396 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
Dintel_dpll.c762 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
1093 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1156 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1178 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1222 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1259 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1296 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1335 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1617 if (pipe_config->port_clock == 162000 || in vlv_prepare_pll()
Dintel_audio.c132 crtc_state->port_clock == dp_aud_n_m[i].clock) in audio_config_dp_get_n_m()
289 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
536 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
574 link_clk = crtc_state->port_clock; in calc_samples_room()
873 crtc_state->port_clock, in intel_audio_codec_enable()
Dintel_snps_phy.c661 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) in intel_mpllb_calc_state()
669 crtc_state->port_clock); in intel_mpllb_calc_state()
679 if (crtc_state->port_clock <= tables[i]->clock) { in intel_mpllb_calc_state()
Dintel_dp.h84 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
Dintel_dpio_phy.c907 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
909 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
911 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
913 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
Dintel_dp_mst.c64 crtc_state->port_clock = limits->max_clock; in intel_dp_mst_compute_link_config()
77 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
94 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
Dintel_dp.c890 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, in intel_dp_compute_rate() argument
897 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
899 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1081 pipe_config->port_clock = link_clock; in intel_dp_compute_link_config_wide()
1215 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; in intel_dp_dsc_compute_config()
1231 pipe_config->port_clock, in intel_dp_dsc_compute_config()
1381 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1389 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1393 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1400 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
[all …]
Dintel_dpll_mgr.c901 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_get_dpll()
966 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1023 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_get_dpll()
1585 if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, in skl_ddi_hdmi_pll_dividers()
1690 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2126 crtc_state->port_clock, in bxt_ddi_hdmi_pll_dividers()
2147 int clock = crtc_state->port_clock; in bxt_ddi_dp_pll_dividers()
2166 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2543 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2626 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
[all …]
Dg4x_hdmi.c121 dotclock = pipe_config->port_clock * 2 / 3; in intel_hdmi_get_config()
123 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
Dintel_crt.c140 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
446 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
Dintel_dvo.c184 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
Dintel_display_types.h1075 int port_clock; member
2055 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
Dintel_hdmi.c2075 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); in intel_hdmi_compute_clock()
2089 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, in intel_hdmi_compute_clock()
2093 crtc_state->port_clock); in intel_hdmi_compute_clock()
2231 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
Dintel_display.c5048 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
5082 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
5236 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
6787 int port_clock; in i9xx_crtc_clock_get() local
6829 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
6831 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
6858 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
6866 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
7802 pipe_config->port_clock, in intel_dump_pipe_config()
8136 pipe_config->port_clock = 0; in intel_modeset_pipe_config()
[all …]
Dintel_tv.c1119 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1207 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
Dintel_cdclk.c2093 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2120 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2347 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
Dintel_lvds.c151 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
Dintel_sdvo.c1257 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1678 dotclock = pipe_config->port_clock; in intel_sdvo_get_config()
Dvlv_dsi.c1278 pipe_config->port_clock = pclk; in intel_dsi_get_config()
Dintel_psr.c844 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
Dicl_dsi.c1684 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()