1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <linux/slab.h>
27
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_mipi_dsi.h>
32
33 #include "i915_drv.h"
34 #include "intel_atomic.h"
35 #include "intel_connector.h"
36 #include "intel_crtc.h"
37 #include "intel_de.h"
38 #include "intel_display_types.h"
39 #include "intel_dsi.h"
40 #include "intel_fifo_underrun.h"
41 #include "intel_panel.h"
42 #include "intel_sideband.h"
43 #include "skl_scaler.h"
44
45 /* return pixels in terms of txbyteclkhs */
txbyteclkhs(u16 pixels,int bpp,int lane_count,u16 burst_mode_ratio)46 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
47 u16 burst_mode_ratio)
48 {
49 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
50 8 * 100), lane_count);
51 }
52
53 /* return pixels equvalent to txbyteclkhs */
pixels_from_txbyteclkhs(u16 clk_hs,int bpp,int lane_count,u16 burst_mode_ratio)54 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
55 u16 burst_mode_ratio)
56 {
57 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
58 (bpp * burst_mode_ratio));
59 }
60
pixel_format_from_register_bits(u32 fmt)61 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
62 {
63 /* It just so happens the VBT matches register contents. */
64 switch (fmt) {
65 case VID_MODE_FORMAT_RGB888:
66 return MIPI_DSI_FMT_RGB888;
67 case VID_MODE_FORMAT_RGB666:
68 return MIPI_DSI_FMT_RGB666;
69 case VID_MODE_FORMAT_RGB666_PACKED:
70 return MIPI_DSI_FMT_RGB666_PACKED;
71 case VID_MODE_FORMAT_RGB565:
72 return MIPI_DSI_FMT_RGB565;
73 default:
74 MISSING_CASE(fmt);
75 return MIPI_DSI_FMT_RGB666;
76 }
77 }
78
vlv_dsi_wait_for_fifo_empty(struct intel_dsi * intel_dsi,enum port port)79 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
80 {
81 struct drm_encoder *encoder = &intel_dsi->base.base;
82 struct drm_device *dev = encoder->dev;
83 struct drm_i915_private *dev_priv = to_i915(dev);
84 u32 mask;
85
86 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
87 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
88
89 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
90 mask, 100))
91 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
92 }
93
write_data(struct drm_i915_private * dev_priv,i915_reg_t reg,const u8 * data,u32 len)94 static void write_data(struct drm_i915_private *dev_priv,
95 i915_reg_t reg,
96 const u8 *data, u32 len)
97 {
98 u32 i, j;
99
100 for (i = 0; i < len; i += 4) {
101 u32 val = 0;
102
103 for (j = 0; j < min_t(u32, len - i, 4); j++)
104 val |= *data++ << 8 * j;
105
106 intel_de_write(dev_priv, reg, val);
107 }
108 }
109
read_data(struct drm_i915_private * dev_priv,i915_reg_t reg,u8 * data,u32 len)110 static void read_data(struct drm_i915_private *dev_priv,
111 i915_reg_t reg,
112 u8 *data, u32 len)
113 {
114 u32 i, j;
115
116 for (i = 0; i < len; i += 4) {
117 u32 val = intel_de_read(dev_priv, reg);
118
119 for (j = 0; j < min_t(u32, len - i, 4); j++)
120 *data++ = val >> 8 * j;
121 }
122 }
123
intel_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)124 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
125 const struct mipi_dsi_msg *msg)
126 {
127 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
128 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
129 struct drm_i915_private *dev_priv = to_i915(dev);
130 enum port port = intel_dsi_host->port;
131 struct mipi_dsi_packet packet;
132 ssize_t ret;
133 const u8 *header, *data;
134 i915_reg_t data_reg, ctrl_reg;
135 u32 data_mask, ctrl_mask;
136
137 ret = mipi_dsi_create_packet(&packet, msg);
138 if (ret < 0)
139 return ret;
140
141 header = packet.header;
142 data = packet.payload;
143
144 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
145 data_reg = MIPI_LP_GEN_DATA(port);
146 data_mask = LP_DATA_FIFO_FULL;
147 ctrl_reg = MIPI_LP_GEN_CTRL(port);
148 ctrl_mask = LP_CTRL_FIFO_FULL;
149 } else {
150 data_reg = MIPI_HS_GEN_DATA(port);
151 data_mask = HS_DATA_FIFO_FULL;
152 ctrl_reg = MIPI_HS_GEN_CTRL(port);
153 ctrl_mask = HS_CTRL_FIFO_FULL;
154 }
155
156 /* note: this is never true for reads */
157 if (packet.payload_length) {
158 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
159 data_mask, 50))
160 drm_err(&dev_priv->drm,
161 "Timeout waiting for HS/LP DATA FIFO !full\n");
162
163 write_data(dev_priv, data_reg, packet.payload,
164 packet.payload_length);
165 }
166
167 if (msg->rx_len) {
168 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
169 GEN_READ_DATA_AVAIL);
170 }
171
172 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
173 ctrl_mask, 50)) {
174 drm_err(&dev_priv->drm,
175 "Timeout waiting for HS/LP CTRL FIFO !full\n");
176 }
177
178 intel_de_write(dev_priv, ctrl_reg,
179 header[2] << 16 | header[1] << 8 | header[0]);
180
181 /* ->rx_len is set only for reads */
182 if (msg->rx_len) {
183 data_mask = GEN_READ_DATA_AVAIL;
184 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
185 data_mask, 50))
186 drm_err(&dev_priv->drm,
187 "Timeout waiting for read data.\n");
188
189 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
190 }
191
192 /* XXX: fix for reads and writes */
193 return 4 + packet.payload_length;
194 }
195
intel_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)196 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
197 struct mipi_dsi_device *dsi)
198 {
199 return 0;
200 }
201
intel_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)202 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
203 struct mipi_dsi_device *dsi)
204 {
205 return 0;
206 }
207
208 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
209 .attach = intel_dsi_host_attach,
210 .detach = intel_dsi_host_detach,
211 .transfer = intel_dsi_host_transfer,
212 };
213
214 /*
215 * send a video mode command
216 *
217 * XXX: commands with data in MIPI_DPI_DATA?
218 */
dpi_send_cmd(struct intel_dsi * intel_dsi,u32 cmd,bool hs,enum port port)219 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
220 enum port port)
221 {
222 struct drm_encoder *encoder = &intel_dsi->base.base;
223 struct drm_device *dev = encoder->dev;
224 struct drm_i915_private *dev_priv = to_i915(dev);
225 u32 mask;
226
227 /* XXX: pipe, hs */
228 if (hs)
229 cmd &= ~DPI_LP_MODE;
230 else
231 cmd |= DPI_LP_MODE;
232
233 /* clear bit */
234 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
235
236 /* XXX: old code skips write if control unchanged */
237 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
238 drm_dbg_kms(&dev_priv->drm,
239 "Same special packet %02x twice in a row.\n", cmd);
240
241 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
242
243 mask = SPL_PKT_SENT_INTERRUPT;
244 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
245 drm_err(&dev_priv->drm,
246 "Video mode command 0x%08x send failed.\n", cmd);
247
248 return 0;
249 }
250
band_gap_reset(struct drm_i915_private * dev_priv)251 static void band_gap_reset(struct drm_i915_private *dev_priv)
252 {
253 vlv_flisdsi_get(dev_priv);
254
255 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
256 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
257 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
258 udelay(150);
259 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
260 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
261
262 vlv_flisdsi_put(dev_priv);
263 }
264
intel_dsi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)265 static int intel_dsi_compute_config(struct intel_encoder *encoder,
266 struct intel_crtc_state *pipe_config,
267 struct drm_connector_state *conn_state)
268 {
269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
270 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
271 base);
272 struct intel_connector *intel_connector = intel_dsi->attached_connector;
273 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
274 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
275 int ret;
276
277 drm_dbg_kms(&dev_priv->drm, "\n");
278 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
279
280 if (fixed_mode) {
281 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
282
283 if (HAS_GMCH(dev_priv))
284 ret = intel_gmch_panel_fitting(pipe_config, conn_state);
285 else
286 ret = intel_pch_panel_fitting(pipe_config, conn_state);
287 if (ret)
288 return ret;
289 }
290
291 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
292 return -EINVAL;
293
294 /* DSI uses short packets for sync events, so clear mode flags for DSI */
295 adjusted_mode->flags = 0;
296
297 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
298 pipe_config->pipe_bpp = 24;
299 else
300 pipe_config->pipe_bpp = 18;
301
302 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
303 /* Enable Frame time stamp based scanline reporting */
304 pipe_config->mode_flags |=
305 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
306
307 /* Dual link goes to DSI transcoder A. */
308 if (intel_dsi->ports == BIT(PORT_C))
309 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
310 else
311 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
312
313 ret = bxt_dsi_pll_compute(encoder, pipe_config);
314 if (ret)
315 return -EINVAL;
316 } else {
317 ret = vlv_dsi_pll_compute(encoder, pipe_config);
318 if (ret)
319 return -EINVAL;
320 }
321
322 pipe_config->clock_set = true;
323
324 return 0;
325 }
326
glk_dsi_enable_io(struct intel_encoder * encoder)327 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
328 {
329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
330 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
331 enum port port;
332 u32 tmp;
333 bool cold_boot = false;
334
335 /* Set the MIPI mode
336 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
337 * Power ON MIPI IO first and then write into IO reset and LP wake bits
338 */
339 for_each_dsi_port(port, intel_dsi->ports) {
340 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
341 intel_de_write(dev_priv, MIPI_CTRL(port),
342 tmp | GLK_MIPIIO_ENABLE);
343 }
344
345 /* Put the IO into reset */
346 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
347 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
348 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
349
350 /* Program LP Wake */
351 for_each_dsi_port(port, intel_dsi->ports) {
352 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
353 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
354 tmp &= ~GLK_LP_WAKE;
355 else
356 tmp |= GLK_LP_WAKE;
357 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
358 }
359
360 /* Wait for Pwr ACK */
361 for_each_dsi_port(port, intel_dsi->ports) {
362 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
363 GLK_MIPIIO_PORT_POWERED, 20))
364 drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
365 }
366
367 /* Check for cold boot scenario */
368 for_each_dsi_port(port, intel_dsi->ports) {
369 cold_boot |=
370 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
371 }
372
373 return cold_boot;
374 }
375
glk_dsi_device_ready(struct intel_encoder * encoder)376 static void glk_dsi_device_ready(struct intel_encoder *encoder)
377 {
378 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
379 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
380 enum port port;
381 u32 val;
382
383 /* Wait for MIPI PHY status bit to set */
384 for_each_dsi_port(port, intel_dsi->ports) {
385 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
386 GLK_PHY_STATUS_PORT_READY, 20))
387 drm_err(&dev_priv->drm, "PHY is not ON\n");
388 }
389
390 /* Get IO out of reset */
391 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
392 intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
393 val | GLK_MIPIIO_RESET_RELEASED);
394
395 /* Get IO out of Low power state*/
396 for_each_dsi_port(port, intel_dsi->ports) {
397 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
398 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
399 val &= ~ULPS_STATE_MASK;
400 val |= DEVICE_READY;
401 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
402 usleep_range(10, 15);
403 } else {
404 /* Enter ULPS */
405 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
406 val &= ~ULPS_STATE_MASK;
407 val |= (ULPS_STATE_ENTER | DEVICE_READY);
408 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
409
410 /* Wait for ULPS active */
411 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
412 GLK_ULPS_NOT_ACTIVE, 20))
413 drm_err(&dev_priv->drm, "ULPS not active\n");
414
415 /* Exit ULPS */
416 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
417 val &= ~ULPS_STATE_MASK;
418 val |= (ULPS_STATE_EXIT | DEVICE_READY);
419 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
420
421 /* Enter Normal Mode */
422 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
423 val &= ~ULPS_STATE_MASK;
424 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
425 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
426
427 val = intel_de_read(dev_priv, MIPI_CTRL(port));
428 val &= ~GLK_LP_WAKE;
429 intel_de_write(dev_priv, MIPI_CTRL(port), val);
430 }
431 }
432
433 /* Wait for Stop state */
434 for_each_dsi_port(port, intel_dsi->ports) {
435 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
436 GLK_DATA_LANE_STOP_STATE, 20))
437 drm_err(&dev_priv->drm,
438 "Date lane not in STOP state\n");
439 }
440
441 /* Wait for AFE LATCH */
442 for_each_dsi_port(port, intel_dsi->ports) {
443 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
444 AFE_LATCHOUT, 20))
445 drm_err(&dev_priv->drm,
446 "D-PHY not entering LP-11 state\n");
447 }
448 }
449
bxt_dsi_device_ready(struct intel_encoder * encoder)450 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
451 {
452 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
453 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
454 enum port port;
455 u32 val;
456
457 drm_dbg_kms(&dev_priv->drm, "\n");
458
459 /* Enable MIPI PHY transparent latch */
460 for_each_dsi_port(port, intel_dsi->ports) {
461 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
462 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port),
463 val | LP_OUTPUT_HOLD);
464 usleep_range(2000, 2500);
465 }
466
467 /* Clear ULPS and set device ready */
468 for_each_dsi_port(port, intel_dsi->ports) {
469 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
470 val &= ~ULPS_STATE_MASK;
471 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
472 usleep_range(2000, 2500);
473 val |= DEVICE_READY;
474 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
475 }
476 }
477
vlv_dsi_device_ready(struct intel_encoder * encoder)478 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
479 {
480 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
481 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
482 enum port port;
483 u32 val;
484
485 drm_dbg_kms(&dev_priv->drm, "\n");
486
487 vlv_flisdsi_get(dev_priv);
488 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
489 * needed everytime after power gate */
490 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
491 vlv_flisdsi_put(dev_priv);
492
493 /* bandgap reset is needed after everytime we do power gate */
494 band_gap_reset(dev_priv);
495
496 for_each_dsi_port(port, intel_dsi->ports) {
497
498 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
499 ULPS_STATE_ENTER);
500 usleep_range(2500, 3000);
501
502 /* Enable MIPI PHY transparent latch
503 * Common bit for both MIPI Port A & MIPI Port C
504 * No similar bit in MIPI Port C reg
505 */
506 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A));
507 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A),
508 val | LP_OUTPUT_HOLD);
509 usleep_range(1000, 1500);
510
511 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
512 ULPS_STATE_EXIT);
513 usleep_range(2500, 3000);
514
515 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
516 DEVICE_READY);
517 usleep_range(2500, 3000);
518 }
519 }
520
intel_dsi_device_ready(struct intel_encoder * encoder)521 static void intel_dsi_device_ready(struct intel_encoder *encoder)
522 {
523 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
524
525 if (IS_GEMINILAKE(dev_priv))
526 glk_dsi_device_ready(encoder);
527 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
528 bxt_dsi_device_ready(encoder);
529 else
530 vlv_dsi_device_ready(encoder);
531 }
532
glk_dsi_enter_low_power_mode(struct intel_encoder * encoder)533 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
534 {
535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
536 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
537 enum port port;
538 u32 val;
539
540 /* Enter ULPS */
541 for_each_dsi_port(port, intel_dsi->ports) {
542 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
543 val &= ~ULPS_STATE_MASK;
544 val |= (ULPS_STATE_ENTER | DEVICE_READY);
545 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
546 }
547
548 /* Wait for MIPI PHY status bit to unset */
549 for_each_dsi_port(port, intel_dsi->ports) {
550 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
551 GLK_PHY_STATUS_PORT_READY, 20))
552 drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
553 }
554
555 /* Wait for Pwr ACK bit to unset */
556 for_each_dsi_port(port, intel_dsi->ports) {
557 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
558 GLK_MIPIIO_PORT_POWERED, 20))
559 drm_err(&dev_priv->drm,
560 "MIPI IO Port is not powergated\n");
561 }
562 }
563
glk_dsi_disable_mipi_io(struct intel_encoder * encoder)564 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
565 {
566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
568 enum port port;
569 u32 tmp;
570
571 /* Put the IO into reset */
572 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
573 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
574 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
575
576 /* Wait for MIPI PHY status bit to unset */
577 for_each_dsi_port(port, intel_dsi->ports) {
578 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
579 GLK_PHY_STATUS_PORT_READY, 20))
580 drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
581 }
582
583 /* Clear MIPI mode */
584 for_each_dsi_port(port, intel_dsi->ports) {
585 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
586 tmp &= ~GLK_MIPIIO_ENABLE;
587 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
588 }
589 }
590
glk_dsi_clear_device_ready(struct intel_encoder * encoder)591 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
592 {
593 glk_dsi_enter_low_power_mode(encoder);
594 glk_dsi_disable_mipi_io(encoder);
595 }
596
vlv_dsi_clear_device_ready(struct intel_encoder * encoder)597 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
598 {
599 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
600 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
601 enum port port;
602
603 drm_dbg_kms(&dev_priv->drm, "\n");
604 for_each_dsi_port(port, intel_dsi->ports) {
605 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
606 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
607 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
608 u32 val;
609
610 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
611 DEVICE_READY | ULPS_STATE_ENTER);
612 usleep_range(2000, 2500);
613
614 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
615 DEVICE_READY | ULPS_STATE_EXIT);
616 usleep_range(2000, 2500);
617
618 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
619 DEVICE_READY | ULPS_STATE_ENTER);
620 usleep_range(2000, 2500);
621
622 /*
623 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
624 * Port A only. MIPI Port C has no similar bit for checking.
625 */
626 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
627 intel_de_wait_for_clear(dev_priv, port_ctrl,
628 AFE_LATCHOUT, 30))
629 drm_err(&dev_priv->drm, "DSI LP not going Low\n");
630
631 /* Disable MIPI PHY transparent latch */
632 val = intel_de_read(dev_priv, port_ctrl);
633 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD);
634 usleep_range(1000, 1500);
635
636 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
637 usleep_range(2000, 2500);
638 }
639 }
640
intel_dsi_port_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)641 static void intel_dsi_port_enable(struct intel_encoder *encoder,
642 const struct intel_crtc_state *crtc_state)
643 {
644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
646 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
647 enum port port;
648
649 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
650 u32 temp;
651 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
652 for_each_dsi_port(port, intel_dsi->ports) {
653 temp = intel_de_read(dev_priv,
654 MIPI_CTRL(port));
655 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
656 intel_dsi->pixel_overlap <<
657 BXT_PIXEL_OVERLAP_CNT_SHIFT;
658 intel_de_write(dev_priv, MIPI_CTRL(port),
659 temp);
660 }
661 } else {
662 temp = intel_de_read(dev_priv, VLV_CHICKEN_3);
663 temp &= ~PIXEL_OVERLAP_CNT_MASK |
664 intel_dsi->pixel_overlap <<
665 PIXEL_OVERLAP_CNT_SHIFT;
666 intel_de_write(dev_priv, VLV_CHICKEN_3, temp);
667 }
668 }
669
670 for_each_dsi_port(port, intel_dsi->ports) {
671 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
672 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
673 u32 temp;
674
675 temp = intel_de_read(dev_priv, port_ctrl);
676
677 temp &= ~LANE_CONFIGURATION_MASK;
678 temp &= ~DUAL_LINK_MODE_MASK;
679
680 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
681 temp |= (intel_dsi->dual_link - 1)
682 << DUAL_LINK_MODE_SHIFT;
683 if (IS_BROXTON(dev_priv))
684 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
685 else
686 temp |= crtc->pipe ?
687 LANE_CONFIGURATION_DUAL_LINK_B :
688 LANE_CONFIGURATION_DUAL_LINK_A;
689 }
690
691 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
692 temp |= DITHERING_ENABLE;
693
694 /* assert ip_tg_enable signal */
695 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
696 intel_de_posting_read(dev_priv, port_ctrl);
697 }
698 }
699
intel_dsi_port_disable(struct intel_encoder * encoder)700 static void intel_dsi_port_disable(struct intel_encoder *encoder)
701 {
702 struct drm_device *dev = encoder->base.dev;
703 struct drm_i915_private *dev_priv = to_i915(dev);
704 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
705 enum port port;
706
707 for_each_dsi_port(port, intel_dsi->ports) {
708 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
709 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
710 u32 temp;
711
712 /* de-assert ip_tg_enable signal */
713 temp = intel_de_read(dev_priv, port_ctrl);
714 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE);
715 intel_de_posting_read(dev_priv, port_ctrl);
716 }
717 }
718
intel_dsi_wait_panel_power_cycle(struct intel_dsi * intel_dsi)719 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
720 {
721 ktime_t panel_power_on_time;
722 s64 panel_power_off_duration;
723
724 panel_power_on_time = ktime_get_boottime();
725 panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
726 intel_dsi->panel_power_off_time);
727
728 if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
729 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
730 }
731
732 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
733 const struct intel_crtc_state *pipe_config);
734 static void intel_dsi_unprepare(struct intel_encoder *encoder);
735
736 /*
737 * Panel enable/disable sequences from the VBT spec.
738 *
739 * Note the spec has AssertReset / DeassertReset swapped from their
740 * usual naming. We use the normal names to avoid confusion (so below
741 * they are swapped compared to the spec).
742 *
743 * Steps starting with MIPI refer to VBT sequences, note that for v2
744 * VBTs several steps which have a VBT in v2 are expected to be handled
745 * directly by the driver, by directly driving gpios for example.
746 *
747 * v2 video mode seq v3 video mode seq command mode seq
748 * - power on - MIPIPanelPowerOn - power on
749 * - wait t1+t2 - wait t1+t2
750 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
751 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
752 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
753 * - MIPITearOn
754 * - MIPIDisplayOn
755 * - turn on DPI - turn on DPI - set pipe to dsr mode
756 * - MIPIDisplayOn - MIPIDisplayOn
757 * - wait t5 - wait t5
758 * - backlight on - MIPIBacklightOn - backlight on
759 * ... ... ... issue mem cmds ...
760 * - backlight off - MIPIBacklightOff - backlight off
761 * - wait t6 - wait t6
762 * - MIPIDisplayOff
763 * - turn off DPI - turn off DPI - disable pipe dsr mode
764 * - MIPITearOff
765 * - MIPIDisplayOff - MIPIDisplayOff
766 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
767 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
768 * - wait t3 - wait t3
769 * - power off - MIPIPanelPowerOff - power off
770 * - wait t4 - wait t4
771 */
772
773 /*
774 * DSI port enable has to be done before pipe and plane enable, so we do it in
775 * the pre_enable hook instead of the enable hook.
776 */
intel_dsi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)777 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
778 struct intel_encoder *encoder,
779 const struct intel_crtc_state *pipe_config,
780 const struct drm_connector_state *conn_state)
781 {
782 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
783 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
784 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
785 enum pipe pipe = crtc->pipe;
786 enum port port;
787 u32 val;
788 bool glk_cold_boot = false;
789
790 drm_dbg_kms(&dev_priv->drm, "\n");
791
792 intel_dsi_wait_panel_power_cycle(intel_dsi);
793
794 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
795
796 /*
797 * The BIOS may leave the PLL in a wonky state where it doesn't
798 * lock. It needs to be fully powered down to fix it.
799 */
800 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
801 bxt_dsi_pll_disable(encoder);
802 bxt_dsi_pll_enable(encoder, pipe_config);
803 } else {
804 vlv_dsi_pll_disable(encoder);
805 vlv_dsi_pll_enable(encoder, pipe_config);
806 }
807
808 if (IS_BROXTON(dev_priv)) {
809 /* Add MIPI IO reset programming for modeset */
810 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
811 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
812 val | MIPIO_RST_CTRL);
813
814 /* Power up DSI regulator */
815 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
816 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
817 }
818
819 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
820 u32 val;
821
822 /* Disable DPOunit clock gating, can stall pipe */
823 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
824 val |= DPOUNIT_CLOCK_GATE_DISABLE;
825 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
826 }
827
828 if (!IS_GEMINILAKE(dev_priv))
829 intel_dsi_prepare(encoder, pipe_config);
830
831 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
832
833 /*
834 * Give the panel time to power-on and then deassert its reset.
835 * Depending on the VBT MIPI sequences version the deassert-seq
836 * may contain the necessary delay, intel_dsi_msleep() will skip
837 * the delay in that case. If there is no deassert-seq, then an
838 * unconditional msleep is used to give the panel time to power-on.
839 */
840 if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
841 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
842 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
843 } else {
844 msleep(intel_dsi->panel_on_delay);
845 }
846
847 if (IS_GEMINILAKE(dev_priv)) {
848 glk_cold_boot = glk_dsi_enable_io(encoder);
849
850 /* Prepare port in cold boot(s3/s4) scenario */
851 if (glk_cold_boot)
852 intel_dsi_prepare(encoder, pipe_config);
853 }
854
855 /* Put device in ready state (LP-11) */
856 intel_dsi_device_ready(encoder);
857
858 /* Prepare port in normal boot scenario */
859 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
860 intel_dsi_prepare(encoder, pipe_config);
861
862 /* Send initialization commands in LP mode */
863 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
864
865 /*
866 * Enable port in pre-enable phase itself because as per hw team
867 * recommendation, port should be enabled before plane & pipe
868 */
869 if (is_cmd_mode(intel_dsi)) {
870 for_each_dsi_port(port, intel_dsi->ports)
871 intel_de_write(dev_priv,
872 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
873 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
874 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
875 } else {
876 msleep(20); /* XXX */
877 for_each_dsi_port(port, intel_dsi->ports)
878 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
879 intel_dsi_msleep(intel_dsi, 100);
880
881 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
882
883 intel_dsi_port_enable(encoder, pipe_config);
884 }
885
886 intel_panel_enable_backlight(pipe_config, conn_state);
887 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
888 }
889
bxt_dsi_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)890 static void bxt_dsi_enable(struct intel_atomic_state *state,
891 struct intel_encoder *encoder,
892 const struct intel_crtc_state *crtc_state,
893 const struct drm_connector_state *conn_state)
894 {
895 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
896
897 intel_crtc_vblank_on(crtc_state);
898 }
899
900 /*
901 * DSI port disable has to be done after pipe and plane disable, so we do it in
902 * the post_disable hook.
903 */
intel_dsi_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)904 static void intel_dsi_disable(struct intel_atomic_state *state,
905 struct intel_encoder *encoder,
906 const struct intel_crtc_state *old_crtc_state,
907 const struct drm_connector_state *old_conn_state)
908 {
909 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
910 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
911 enum port port;
912
913 drm_dbg_kms(&i915->drm, "\n");
914
915 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
916 intel_panel_disable_backlight(old_conn_state);
917
918 /*
919 * According to the spec we should send SHUTDOWN before
920 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
921 * has shown that the v3 sequence works for v2 VBTs too
922 */
923 if (is_vid_mode(intel_dsi)) {
924 /* Send Shutdown command to the panel in LP mode */
925 for_each_dsi_port(port, intel_dsi->ports)
926 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
927 msleep(10);
928 }
929 }
930
intel_dsi_clear_device_ready(struct intel_encoder * encoder)931 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
932 {
933 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
934
935 if (IS_GEMINILAKE(dev_priv))
936 glk_dsi_clear_device_ready(encoder);
937 else
938 vlv_dsi_clear_device_ready(encoder);
939 }
940
intel_dsi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)941 static void intel_dsi_post_disable(struct intel_atomic_state *state,
942 struct intel_encoder *encoder,
943 const struct intel_crtc_state *old_crtc_state,
944 const struct drm_connector_state *old_conn_state)
945 {
946 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
947 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
948 enum port port;
949 u32 val;
950
951 drm_dbg_kms(&dev_priv->drm, "\n");
952
953 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
954 intel_crtc_vblank_off(old_crtc_state);
955
956 skl_scaler_disable(old_crtc_state);
957 }
958
959 if (is_vid_mode(intel_dsi)) {
960 for_each_dsi_port(port, intel_dsi->ports)
961 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
962
963 intel_dsi_port_disable(encoder);
964 usleep_range(2000, 5000);
965 }
966
967 intel_dsi_unprepare(encoder);
968
969 /*
970 * if disable packets are sent before sending shutdown packet then in
971 * some next enable sequence send turn on packet error is observed
972 */
973 if (is_cmd_mode(intel_dsi))
974 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
975 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
976
977 /* Transition to LP-00 */
978 intel_dsi_clear_device_ready(encoder);
979
980 if (IS_BROXTON(dev_priv)) {
981 /* Power down DSI regulator to save power */
982 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
983 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
984 HS_IO_CTRL_SELECT);
985
986 /* Add MIPI IO reset programming for modeset */
987 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
988 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
989 val & ~MIPIO_RST_CTRL);
990 }
991
992 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
993 bxt_dsi_pll_disable(encoder);
994 } else {
995 u32 val;
996
997 vlv_dsi_pll_disable(encoder);
998
999 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
1000 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
1001 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
1002 }
1003
1004 /* Assert reset */
1005 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1006
1007 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
1008 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1009
1010 intel_dsi->panel_power_off_time = ktime_get_boottime();
1011 }
1012
intel_dsi_shutdown(struct intel_encoder * encoder)1013 static void intel_dsi_shutdown(struct intel_encoder *encoder)
1014 {
1015 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1016
1017 intel_dsi_wait_panel_power_cycle(intel_dsi);
1018 }
1019
intel_dsi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)1020 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1021 enum pipe *pipe)
1022 {
1023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1024 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1025 intel_wakeref_t wakeref;
1026 enum port port;
1027 bool active = false;
1028
1029 drm_dbg_kms(&dev_priv->drm, "\n");
1030
1031 wakeref = intel_display_power_get_if_enabled(dev_priv,
1032 encoder->power_domain);
1033 if (!wakeref)
1034 return false;
1035
1036 /*
1037 * On Broxton the PLL needs to be enabled with a valid divider
1038 * configuration, otherwise accessing DSI registers will hang the
1039 * machine. See BSpec North Display Engine registers/MIPI[BXT].
1040 */
1041 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1042 !bxt_dsi_pll_is_enabled(dev_priv))
1043 goto out_put_power;
1044
1045 /* XXX: this only works for one DSI output */
1046 for_each_dsi_port(port, intel_dsi->ports) {
1047 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
1048 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1049 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
1050
1051 /*
1052 * Due to some hardware limitations on VLV/CHV, the DPI enable
1053 * bit in port C control register does not get set. As a
1054 * workaround, check pipe B conf instead.
1055 */
1056 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1057 port == PORT_C)
1058 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1059
1060 /* Try command mode if video mode not enabled */
1061 if (!enabled) {
1062 u32 tmp = intel_de_read(dev_priv,
1063 MIPI_DSI_FUNC_PRG(port));
1064 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1065 }
1066
1067 if (!enabled)
1068 continue;
1069
1070 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1071 continue;
1072
1073 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1074 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1075 tmp &= BXT_PIPE_SELECT_MASK;
1076 tmp >>= BXT_PIPE_SELECT_SHIFT;
1077
1078 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1079 continue;
1080
1081 *pipe = tmp;
1082 } else {
1083 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1084 }
1085
1086 active = true;
1087 break;
1088 }
1089
1090 out_put_power:
1091 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1092
1093 return active;
1094 }
1095
bxt_dsi_get_pipe_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1096 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1097 struct intel_crtc_state *pipe_config)
1098 {
1099 struct drm_device *dev = encoder->base.dev;
1100 struct drm_i915_private *dev_priv = to_i915(dev);
1101 struct drm_display_mode *adjusted_mode =
1102 &pipe_config->hw.adjusted_mode;
1103 struct drm_display_mode *adjusted_mode_sw;
1104 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1105 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1106 unsigned int lane_count = intel_dsi->lane_count;
1107 unsigned int bpp, fmt;
1108 enum port port;
1109 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1110 u16 hfp_sw, hsync_sw, hbp_sw;
1111 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1112 crtc_hblank_start_sw, crtc_hblank_end_sw;
1113
1114 /* FIXME: hw readout should not depend on SW state */
1115 adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1116
1117 /*
1118 * Atleast one port is active as encoder->get_config called only if
1119 * encoder->get_hw_state() returns true.
1120 */
1121 for_each_dsi_port(port, intel_dsi->ports) {
1122 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1123 break;
1124 }
1125
1126 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1127 bpp = mipi_dsi_pixel_format_to_bpp(
1128 pixel_format_from_register_bits(fmt));
1129
1130 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1131
1132 /* Enable Frame time stamo based scanline reporting */
1133 pipe_config->mode_flags |=
1134 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1135
1136 /* In terms of pixels */
1137 adjusted_mode->crtc_hdisplay =
1138 intel_de_read(dev_priv,
1139 BXT_MIPI_TRANS_HACTIVE(port));
1140 adjusted_mode->crtc_vdisplay =
1141 intel_de_read(dev_priv,
1142 BXT_MIPI_TRANS_VACTIVE(port));
1143 adjusted_mode->crtc_vtotal =
1144 intel_de_read(dev_priv,
1145 BXT_MIPI_TRANS_VTOTAL(port));
1146
1147 hactive = adjusted_mode->crtc_hdisplay;
1148 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1149
1150 /*
1151 * Meaningful for video mode non-burst sync pulse mode only,
1152 * can be zero for non-burst sync events and burst modes
1153 */
1154 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1155 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1156
1157 /* harizontal values are in terms of high speed byte clock */
1158 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1159 intel_dsi->burst_mode_ratio);
1160 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1161 intel_dsi->burst_mode_ratio);
1162 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1163 intel_dsi->burst_mode_ratio);
1164
1165 if (intel_dsi->dual_link) {
1166 hfp *= 2;
1167 hsync *= 2;
1168 hbp *= 2;
1169 }
1170
1171 /* vertical values are in terms of lines */
1172 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1173 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1174 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port));
1175
1176 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1177 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1178 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1179 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1180 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1181
1182 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1183 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1184 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1185 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1186
1187 /*
1188 * In BXT DSI there is no regs programmed with few horizontal timings
1189 * in Pixels but txbyteclkhs.. So retrieval process adds some
1190 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1191 * Actually here for the given adjusted_mode, we are calculating the
1192 * value programmed to the port and then back to the horizontal timing
1193 * param in pixels. This is the expected value, including roundup errors
1194 * And if that is same as retrieved value from port, then
1195 * (HW state) adjusted_mode's horizontal timings are corrected to
1196 * match with SW state to nullify the errors.
1197 */
1198 /* Calculating the value programmed to the Port register */
1199 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1200 adjusted_mode_sw->crtc_hdisplay;
1201 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1202 adjusted_mode_sw->crtc_hsync_start;
1203 hbp_sw = adjusted_mode_sw->crtc_htotal -
1204 adjusted_mode_sw->crtc_hsync_end;
1205
1206 if (intel_dsi->dual_link) {
1207 hfp_sw /= 2;
1208 hsync_sw /= 2;
1209 hbp_sw /= 2;
1210 }
1211
1212 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1213 intel_dsi->burst_mode_ratio);
1214 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1215 intel_dsi->burst_mode_ratio);
1216 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1217 intel_dsi->burst_mode_ratio);
1218
1219 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1220 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1221 intel_dsi->burst_mode_ratio);
1222 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1223 intel_dsi->burst_mode_ratio);
1224 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1225 intel_dsi->burst_mode_ratio);
1226
1227 if (intel_dsi->dual_link) {
1228 hfp_sw *= 2;
1229 hsync_sw *= 2;
1230 hbp_sw *= 2;
1231 }
1232
1233 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1234 hsync_sw + hbp_sw;
1235 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1236 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1237 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1238 crtc_hblank_end_sw = crtc_htotal_sw;
1239
1240 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1241 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1242
1243 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1244 adjusted_mode->crtc_hsync_start =
1245 adjusted_mode_sw->crtc_hsync_start;
1246
1247 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1248 adjusted_mode->crtc_hsync_end =
1249 adjusted_mode_sw->crtc_hsync_end;
1250
1251 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1252 adjusted_mode->crtc_hblank_start =
1253 adjusted_mode_sw->crtc_hblank_start;
1254
1255 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1256 adjusted_mode->crtc_hblank_end =
1257 adjusted_mode_sw->crtc_hblank_end;
1258 }
1259
intel_dsi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1260 static void intel_dsi_get_config(struct intel_encoder *encoder,
1261 struct intel_crtc_state *pipe_config)
1262 {
1263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1264 u32 pclk;
1265 drm_dbg_kms(&dev_priv->drm, "\n");
1266
1267 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1268
1269 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1270 bxt_dsi_get_pipe_config(encoder, pipe_config);
1271 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1272 } else {
1273 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1274 }
1275
1276 if (pclk) {
1277 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1278 pipe_config->port_clock = pclk;
1279 }
1280 }
1281
1282 /* return txclkesc cycles in terms of divider and duration in us */
txclkesc(u32 divider,unsigned int us)1283 static u16 txclkesc(u32 divider, unsigned int us)
1284 {
1285 switch (divider) {
1286 case ESCAPE_CLOCK_DIVIDER_1:
1287 default:
1288 return 20 * us;
1289 case ESCAPE_CLOCK_DIVIDER_2:
1290 return 10 * us;
1291 case ESCAPE_CLOCK_DIVIDER_4:
1292 return 5 * us;
1293 }
1294 }
1295
set_dsi_timings(struct drm_encoder * encoder,const struct drm_display_mode * adjusted_mode)1296 static void set_dsi_timings(struct drm_encoder *encoder,
1297 const struct drm_display_mode *adjusted_mode)
1298 {
1299 struct drm_device *dev = encoder->dev;
1300 struct drm_i915_private *dev_priv = to_i915(dev);
1301 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1302 enum port port;
1303 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1304 unsigned int lane_count = intel_dsi->lane_count;
1305
1306 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1307
1308 hactive = adjusted_mode->crtc_hdisplay;
1309 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1310 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1311 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1312
1313 if (intel_dsi->dual_link) {
1314 hactive /= 2;
1315 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1316 hactive += intel_dsi->pixel_overlap;
1317 hfp /= 2;
1318 hsync /= 2;
1319 hbp /= 2;
1320 }
1321
1322 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1323 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1324 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1325
1326 /* horizontal values are in terms of high speed byte clock */
1327 hactive = txbyteclkhs(hactive, bpp, lane_count,
1328 intel_dsi->burst_mode_ratio);
1329 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1330 hsync = txbyteclkhs(hsync, bpp, lane_count,
1331 intel_dsi->burst_mode_ratio);
1332 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1333
1334 for_each_dsi_port(port, intel_dsi->ports) {
1335 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1336 /*
1337 * Program hdisplay and vdisplay on MIPI transcoder.
1338 * This is different from calculated hactive and
1339 * vactive, as they are calculated per channel basis,
1340 * whereas these values should be based on resolution.
1341 */
1342 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1343 adjusted_mode->crtc_hdisplay);
1344 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1345 adjusted_mode->crtc_vdisplay);
1346 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1347 adjusted_mode->crtc_vtotal);
1348 }
1349
1350 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1351 hactive);
1352 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1353
1354 /* meaningful for video mode non-burst sync pulse mode only,
1355 * can be zero for non-burst sync events and burst modes */
1356 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1357 hsync);
1358 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1359
1360 /* vertical values are in terms of lines */
1361 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1362 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1363 vsync);
1364 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1365 }
1366 }
1367
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)1368 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1369 {
1370 switch (fmt) {
1371 case MIPI_DSI_FMT_RGB888:
1372 return VID_MODE_FORMAT_RGB888;
1373 case MIPI_DSI_FMT_RGB666:
1374 return VID_MODE_FORMAT_RGB666;
1375 case MIPI_DSI_FMT_RGB666_PACKED:
1376 return VID_MODE_FORMAT_RGB666_PACKED;
1377 case MIPI_DSI_FMT_RGB565:
1378 return VID_MODE_FORMAT_RGB565;
1379 default:
1380 MISSING_CASE(fmt);
1381 return VID_MODE_FORMAT_RGB666;
1382 }
1383 }
1384
intel_dsi_prepare(struct intel_encoder * intel_encoder,const struct intel_crtc_state * pipe_config)1385 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1386 const struct intel_crtc_state *pipe_config)
1387 {
1388 struct drm_encoder *encoder = &intel_encoder->base;
1389 struct drm_device *dev = encoder->dev;
1390 struct drm_i915_private *dev_priv = to_i915(dev);
1391 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1392 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1393 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1394 enum port port;
1395 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1396 u32 val, tmp;
1397 u16 mode_hdisplay;
1398
1399 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1400
1401 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1402
1403 if (intel_dsi->dual_link) {
1404 mode_hdisplay /= 2;
1405 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1406 mode_hdisplay += intel_dsi->pixel_overlap;
1407 }
1408
1409 for_each_dsi_port(port, intel_dsi->ports) {
1410 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1411 /*
1412 * escape clock divider, 20MHz, shared for A and C.
1413 * device ready must be off when doing this! txclkesc?
1414 */
1415 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1416 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1417 intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1418 tmp | ESCAPE_CLOCK_DIVIDER_1);
1419
1420 /* read request priority is per pipe */
1421 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1422 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1423 intel_de_write(dev_priv, MIPI_CTRL(port),
1424 tmp | READ_REQUEST_PRIORITY_HIGH);
1425 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1426 enum pipe pipe = crtc->pipe;
1427
1428 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1429 tmp &= ~BXT_PIPE_SELECT_MASK;
1430
1431 tmp |= BXT_PIPE_SELECT(pipe);
1432 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
1433 }
1434
1435 /* XXX: why here, why like this? handling in irq handler?! */
1436 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1437 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1438
1439 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1440 intel_dsi->dphy_reg);
1441
1442 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1443 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1444 }
1445
1446 set_dsi_timings(encoder, adjusted_mode);
1447
1448 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1449 if (is_cmd_mode(intel_dsi)) {
1450 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1451 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1452 } else {
1453 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1454 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1455 }
1456
1457 tmp = 0;
1458 if (intel_dsi->eotp_pkt == 0)
1459 tmp |= EOT_DISABLE;
1460 if (intel_dsi->clock_stop)
1461 tmp |= CLOCKSTOP;
1462
1463 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1464 tmp |= BXT_DPHY_DEFEATURE_EN;
1465 if (!is_cmd_mode(intel_dsi))
1466 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1467 }
1468
1469 for_each_dsi_port(port, intel_dsi->ports) {
1470 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1471
1472 /* timeouts for recovery. one frame IIUC. if counter expires,
1473 * EOT and stop state. */
1474
1475 /*
1476 * In burst mode, value greater than one DPI line Time in byte
1477 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1478 * said value is recommended.
1479 *
1480 * In non-burst mode, Value greater than one DPI frame time in
1481 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1482 * said value is recommended.
1483 *
1484 * In DBI only mode, value greater than one DBI frame time in
1485 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1486 * said value is recommended.
1487 */
1488
1489 if (is_vid_mode(intel_dsi) &&
1490 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1491 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1492 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1493 } else {
1494 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1495 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1496 }
1497 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1498 intel_dsi->lp_rx_timeout);
1499 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1500 intel_dsi->turn_arnd_val);
1501 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1502 intel_dsi->rst_timer_val);
1503
1504 /* dphy stuff */
1505
1506 /* in terms of low power clock */
1507 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1508 txclkesc(intel_dsi->escape_clk_div, 100));
1509
1510 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1511 !intel_dsi->dual_link) {
1512 /*
1513 * BXT spec says write MIPI_INIT_COUNT for
1514 * both the ports, even if only one is
1515 * getting used. So write the other port
1516 * if not in dual link mode.
1517 */
1518 intel_de_write(dev_priv,
1519 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1520 intel_dsi->init_count);
1521 }
1522
1523 /* recovery disables */
1524 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1525
1526 /* in terms of low power clock */
1527 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1528 intel_dsi->init_count);
1529
1530 /* in terms of txbyteclkhs. actual high to low switch +
1531 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1532 *
1533 * XXX: write MIPI_STOP_STATE_STALL?
1534 */
1535 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1536 intel_dsi->hs_to_lp_count);
1537
1538 /* XXX: low power clock equivalence in terms of byte clock.
1539 * the number of byte clocks occupied in one low power clock.
1540 * based on txbyteclkhs and txclkesc.
1541 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1542 * ) / 105.???
1543 */
1544 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1545 intel_dsi->lp_byte_clk);
1546
1547 if (IS_GEMINILAKE(dev_priv)) {
1548 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1549 intel_dsi->lp_byte_clk);
1550 /* Shadow of DPHY reg */
1551 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1552 intel_dsi->dphy_reg);
1553 }
1554
1555 /* the bw essential for transmitting 16 long packets containing
1556 * 252 bytes meant for dcs write memory command is programmed in
1557 * this register in terms of byte clocks. based on dsi transfer
1558 * rate and the number of lanes configured the time taken to
1559 * transmit 16 long packets in a dsi stream varies. */
1560 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1561 intel_dsi->bw_timer);
1562
1563 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1564 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1565
1566 if (is_vid_mode(intel_dsi))
1567 /* Some panels might have resolution which is not a
1568 * multiple of 64 like 1366 x 768. Enable RANDOM
1569 * resolution support for such panels by default */
1570 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port),
1571 intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION);
1572 }
1573 }
1574
intel_dsi_unprepare(struct intel_encoder * encoder)1575 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1576 {
1577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1578 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1579 enum port port;
1580 u32 val;
1581
1582 if (IS_GEMINILAKE(dev_priv))
1583 return;
1584
1585 for_each_dsi_port(port, intel_dsi->ports) {
1586 /* Panel commands can be sent when clock is in LP11 */
1587 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1588
1589 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1590 bxt_dsi_reset_clocks(encoder, port);
1591 else
1592 vlv_dsi_reset_clocks(encoder, port);
1593 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1594
1595 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port));
1596 val &= ~VID_MODE_FORMAT_MASK;
1597 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1598
1599 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1600 }
1601 }
1602
intel_dsi_encoder_destroy(struct drm_encoder * encoder)1603 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1604 {
1605 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1606
1607 intel_dsi_vbt_gpio_cleanup(intel_dsi);
1608 intel_encoder_destroy(encoder);
1609 }
1610
1611 static const struct drm_encoder_funcs intel_dsi_funcs = {
1612 .destroy = intel_dsi_encoder_destroy,
1613 };
1614
1615 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1616 .get_modes = intel_dsi_get_modes,
1617 .mode_valid = intel_dsi_mode_valid,
1618 .atomic_check = intel_digital_connector_atomic_check,
1619 };
1620
1621 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1622 .detect = intel_panel_detect,
1623 .late_register = intel_connector_register,
1624 .early_unregister = intel_connector_unregister,
1625 .destroy = intel_connector_destroy,
1626 .fill_modes = drm_helper_probe_single_connector_modes,
1627 .atomic_get_property = intel_digital_connector_atomic_get_property,
1628 .atomic_set_property = intel_digital_connector_atomic_set_property,
1629 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1630 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1631 };
1632
vlv_dsi_add_properties(struct intel_connector * connector)1633 static void vlv_dsi_add_properties(struct intel_connector *connector)
1634 {
1635 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1636
1637 if (connector->panel.fixed_mode) {
1638 u32 allowed_scalers;
1639
1640 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1641 if (!HAS_GMCH(dev_priv))
1642 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1643
1644 drm_connector_attach_scaling_mode_property(&connector->base,
1645 allowed_scalers);
1646
1647 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1648
1649 drm_connector_set_panel_orientation_with_quirk(
1650 &connector->base,
1651 intel_dsi_get_panel_orientation(connector),
1652 connector->panel.fixed_mode->hdisplay,
1653 connector->panel.fixed_mode->vdisplay);
1654 }
1655 }
1656
1657 #define NS_KHZ_RATIO 1000000
1658
1659 #define PREPARE_CNT_MAX 0x3F
1660 #define EXIT_ZERO_CNT_MAX 0x3F
1661 #define CLK_ZERO_CNT_MAX 0xFF
1662 #define TRAIL_CNT_MAX 0x1F
1663
vlv_dphy_param_init(struct intel_dsi * intel_dsi)1664 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1665 {
1666 struct drm_device *dev = intel_dsi->base.base.dev;
1667 struct drm_i915_private *dev_priv = to_i915(dev);
1668 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1669 u32 tlpx_ns, extra_byte_count, tlpx_ui;
1670 u32 ui_num, ui_den;
1671 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1672 u32 ths_prepare_ns, tclk_trail_ns;
1673 u32 tclk_prepare_clkzero, ths_prepare_hszero;
1674 u32 lp_to_hs_switch, hs_to_lp_switch;
1675 u32 mul;
1676
1677 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1678
1679 switch (intel_dsi->lane_count) {
1680 case 1:
1681 case 2:
1682 extra_byte_count = 2;
1683 break;
1684 case 3:
1685 extra_byte_count = 4;
1686 break;
1687 case 4:
1688 default:
1689 extra_byte_count = 3;
1690 break;
1691 }
1692
1693 /* in Kbps */
1694 ui_num = NS_KHZ_RATIO;
1695 ui_den = intel_dsi_bitrate(intel_dsi);
1696
1697 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1698 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1699
1700 /*
1701 * B060
1702 * LP byte clock = TLPX/ (8UI)
1703 */
1704 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1705
1706 /* DDR clock period = 2 * UI
1707 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1708 * UI(nsec) = 10^6 / bitrate
1709 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1710 * DDR clock count = ns_value / DDR clock period
1711 *
1712 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1713 * HS byte clock count for other platform in HS ddr clock count
1714 */
1715 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1716 ths_prepare_ns = max(mipi_config->ths_prepare,
1717 mipi_config->tclk_prepare);
1718
1719 /* prepare count */
1720 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1721
1722 if (prepare_cnt > PREPARE_CNT_MAX) {
1723 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1724 prepare_cnt);
1725 prepare_cnt = PREPARE_CNT_MAX;
1726 }
1727
1728 /* exit zero count */
1729 exit_zero_cnt = DIV_ROUND_UP(
1730 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1731 ui_num * mul
1732 );
1733
1734 /*
1735 * Exit zero is unified val ths_zero and ths_exit
1736 * minimum value for ths_exit = 110ns
1737 * min (exit_zero_cnt * 2) = 110/UI
1738 * exit_zero_cnt = 55/UI
1739 */
1740 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1741 exit_zero_cnt += 1;
1742
1743 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1744 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1745 exit_zero_cnt);
1746 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1747 }
1748
1749 /* clk zero count */
1750 clk_zero_cnt = DIV_ROUND_UP(
1751 (tclk_prepare_clkzero - ths_prepare_ns)
1752 * ui_den, ui_num * mul);
1753
1754 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1755 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1756 clk_zero_cnt);
1757 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1758 }
1759
1760 /* trail count */
1761 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1762 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1763
1764 if (trail_cnt > TRAIL_CNT_MAX) {
1765 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1766 trail_cnt);
1767 trail_cnt = TRAIL_CNT_MAX;
1768 }
1769
1770 /* B080 */
1771 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1772 clk_zero_cnt << 8 | prepare_cnt;
1773
1774 /*
1775 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1776 * mul + 10UI + Extra Byte Count
1777 *
1778 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1779 * Extra Byte Count is calculated according to number of lanes.
1780 * High Low Switch Count is the Max of LP to HS and
1781 * HS to LP switch count
1782 *
1783 */
1784 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1785
1786 /* B044 */
1787 /* FIXME:
1788 * The comment above does not match with the code */
1789 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1790 exit_zero_cnt * mul + 10, 8);
1791
1792 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1793
1794 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1795 intel_dsi->hs_to_lp_count += extra_byte_count;
1796
1797 /* B088 */
1798 /* LP -> HS for clock lanes
1799 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1800 * extra byte count
1801 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1802 * 2(in UI) + extra byte count
1803 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1804 * 8 + extra byte count
1805 */
1806 intel_dsi->clk_lp_to_hs_count =
1807 DIV_ROUND_UP(
1808 4 * tlpx_ui + prepare_cnt * 2 +
1809 clk_zero_cnt * 2,
1810 8);
1811
1812 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1813
1814 /* HS->LP for Clock Lanes
1815 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1816 * Extra byte count
1817 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1818 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1819 * Extra byte count
1820 */
1821 intel_dsi->clk_hs_to_lp_count =
1822 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1823 8);
1824 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1825
1826 intel_dsi_log_params(intel_dsi);
1827 }
1828
vlv_dsi_init(struct drm_i915_private * dev_priv)1829 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1830 {
1831 struct drm_device *dev = &dev_priv->drm;
1832 struct intel_dsi *intel_dsi;
1833 struct intel_encoder *intel_encoder;
1834 struct drm_encoder *encoder;
1835 struct intel_connector *intel_connector;
1836 struct drm_connector *connector;
1837 struct drm_display_mode *current_mode, *fixed_mode;
1838 enum port port;
1839 enum pipe pipe;
1840
1841 drm_dbg_kms(&dev_priv->drm, "\n");
1842
1843 /* There is no detection method for MIPI so rely on VBT */
1844 if (!intel_bios_is_dsi_present(dev_priv, &port))
1845 return;
1846
1847 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1848 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1849 else
1850 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1851
1852 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1853 if (!intel_dsi)
1854 return;
1855
1856 intel_connector = intel_connector_alloc();
1857 if (!intel_connector) {
1858 kfree(intel_dsi);
1859 return;
1860 }
1861
1862 intel_encoder = &intel_dsi->base;
1863 encoder = &intel_encoder->base;
1864 intel_dsi->attached_connector = intel_connector;
1865
1866 connector = &intel_connector->base;
1867
1868 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1869 "DSI %c", port_name(port));
1870
1871 intel_encoder->compute_config = intel_dsi_compute_config;
1872 intel_encoder->pre_enable = intel_dsi_pre_enable;
1873 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1874 intel_encoder->enable = bxt_dsi_enable;
1875 intel_encoder->disable = intel_dsi_disable;
1876 intel_encoder->post_disable = intel_dsi_post_disable;
1877 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1878 intel_encoder->get_config = intel_dsi_get_config;
1879 intel_encoder->update_pipe = intel_panel_update_backlight;
1880 intel_encoder->shutdown = intel_dsi_shutdown;
1881
1882 intel_connector->get_hw_state = intel_connector_get_hw_state;
1883
1884 intel_encoder->port = port;
1885 intel_encoder->type = INTEL_OUTPUT_DSI;
1886 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1887 intel_encoder->cloneable = 0;
1888
1889 /*
1890 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1891 * port C. BXT isn't limited like this.
1892 */
1893 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1894 intel_encoder->pipe_mask = ~0;
1895 else if (port == PORT_A)
1896 intel_encoder->pipe_mask = BIT(PIPE_A);
1897 else
1898 intel_encoder->pipe_mask = BIT(PIPE_B);
1899
1900 intel_dsi->panel_power_off_time = ktime_get_boottime();
1901
1902 if (dev_priv->vbt.dsi.config->dual_link)
1903 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1904 else
1905 intel_dsi->ports = BIT(port);
1906
1907 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1908 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1909
1910 /* Create a DSI host (and a device) for each port. */
1911 for_each_dsi_port(port, intel_dsi->ports) {
1912 struct intel_dsi_host *host;
1913
1914 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1915 port);
1916 if (!host)
1917 goto err;
1918
1919 intel_dsi->dsi_hosts[port] = host;
1920 }
1921
1922 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1923 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1924 goto err;
1925 }
1926
1927 /* Use clock read-back from current hw-state for fastboot */
1928 current_mode = intel_encoder_current_mode(intel_encoder);
1929 if (current_mode) {
1930 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1931 intel_dsi->pclk, current_mode->clock);
1932 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1933 current_mode->clock)) {
1934 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1935 intel_dsi->pclk = current_mode->clock;
1936 }
1937
1938 kfree(current_mode);
1939 }
1940
1941 vlv_dphy_param_init(intel_dsi);
1942
1943 intel_dsi_vbt_gpio_init(intel_dsi,
1944 intel_dsi_get_hw_state(intel_encoder, &pipe));
1945
1946 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1947 DRM_MODE_CONNECTOR_DSI);
1948
1949 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1950
1951 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1952 connector->interlace_allowed = false;
1953 connector->doublescan_allowed = false;
1954
1955 intel_connector_attach_encoder(intel_connector, intel_encoder);
1956
1957 mutex_lock(&dev->mode_config.mutex);
1958 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1959 mutex_unlock(&dev->mode_config.mutex);
1960
1961 if (!fixed_mode) {
1962 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1963 goto err_cleanup_connector;
1964 }
1965
1966 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1967 intel_panel_setup_backlight(connector, INVALID_PIPE);
1968
1969 vlv_dsi_add_properties(intel_connector);
1970
1971 return;
1972
1973 err_cleanup_connector:
1974 drm_connector_cleanup(&intel_connector->base);
1975 err:
1976 drm_encoder_cleanup(&intel_encoder->base);
1977 kfree(intel_dsi);
1978 kfree(intel_connector);
1979 }
1980
