216 	int clock = crtc_state->port_clock;  in icl_pll_to_ddi_clk_sel()
251 static u32 ddi_buf_phy_link_rate(int port_clock)  in ddi_buf_phy_link_rate()  argument
253 	switch (port_clock) {  in ddi_buf_phy_link_rate()
271 		MISSING_CASE(port_clock);  in ddi_buf_phy_link_rate()
289 		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);  in intel_ddi_init_dp_buf_reg()
322 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in ddi_dotclock_get()
325 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in ddi_dotclock_get()
328 		dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;  in ddi_dotclock_get()
330 		dotclock = pipe_config->port_clock;  in ddi_dotclock_get()
1098 	rate = crtc_state->port_clock;  in icl_combo_phy_ddi_vswing_sequence()
1226 		if (crtc_state->port_clock < 300000)  in icl_mg_phy_ddi_vswing_sequence()
1237 		if (crtc_state->port_clock <= 500000) {  in icl_mg_phy_ddi_vswing_sequence()
1247 		if (crtc_state->port_clock <= 500000) {  in icl_mg_phy_ddi_vswing_sequence()
1334 		     crtc_state->port_clock == 162000) ||  in tgl_dkl_phy_ddi_vswing_sequence()
1336 		     crtc_state->port_clock == 594000))  in tgl_dkl_phy_ddi_vswing_sequence()
2337 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,  in dg2_ddi_pre_enable_dp()
2448 				 crtc_state->port_clock,  in tgl_ddi_pre_enable_dp()
2597 				 crtc_state->port_clock,  in hsw_ddi_pre_enable_dp()
3431 	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
3433 	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
3435 	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
3706 	crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,  in intel_ddi_get_clock()
3714 	crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);  in dg2_ddi_get_config()
3773 		crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);  in icl_ddi_tc_get_clock()
3775 		crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,  in icl_ddi_tc_get_clock()
3910 		crtc_state1->port_clock == crtc_state2->port_clock &&  in crtcs_port_sync_compatible()