/Linux-v5.15/Documentation/devicetree/bindings/clock/ti/ |
D | dpll.txt | 1 Binding for Texas Instruments DPLL clock. 6 register-mapped DPLL with usually two selectable input clocks 12 for the actual DPLL clock. 39 - reg : offsets for the register set for controlling the DPLL. 45 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains 47 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains 54 - DPLL mode setting - defining any one or more of the following overrides 56 - ti,low-power-stop : DPLL supports low power stop mode, gating output 57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock 58 - ti,lock : DPLL locks in programmed rate [all …]
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D | apll.txt | 11 a subtype of a DPLL [2], although a simplified one at that.
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/Linux-v5.15/drivers/gpu/drm/i915/display/ |
D | intel_dpll.c | 1380 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll() 1457 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll() 1458 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll() 1461 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll() 1508 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll() 1511 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll() 1547 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll() 1567 intel_de_write(dev_priv, DPLL(pipe), in vlv_prepare_pll() 1668 intel_de_write(dev_priv, DPLL(pipe), in chv_prepare_pll() 1811 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_disable_pll() [all …]
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D | intel_dvo.c | 491 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init() 492 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init() 500 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
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D | intel_display.c | 474 val = intel_de_read(dev_priv, DPLL(pipe)); in assert_pll() 763 dpll_reg = DPLL(0); in vlv_wait_port_ready() 767 dpll_reg = DPLL(0); in vlv_wait_port_ready() 5199 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config() 5210 DPLL(crtc->pipe)); in i9xx_get_pipe_config() 12682 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe() 12683 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe() 12686 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe() 12694 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe() 12698 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe() [all …]
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D | intel_display_power.c | 1418 u32 val = intel_de_read(dev_priv, DPLL(pipe)); in vlv_display_power_well_init() 1424 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_display_power_well_init() 1581 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status() 5903 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); in chv_phy_control_init()
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D | intel_pps.c | 81 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
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/Linux-v5.15/include/dt-bindings/clock/ |
D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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/Linux-v5.15/arch/arm/mach-omap2/ |
D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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/Linux-v5.15/arch/arm/boot/dts/ |
D | exynos5422-odroid-core.dtsi | 97 /* derived from 600MHz DPLL */ 199 /* derived from 600MHz DPLL */ 235 /* derived from 600MHz DPLL */ 247 /* derived from 600MHz DPLL */ 262 /* derived from 600MHz DPLL */
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D | rk3036.dtsi | 237 * Fix the emac parent clock is DPLL instead of APLL.
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/Linux-v5.15/Documentation/devicetree/bindings/phy/ |
D | ti-phy.txt | 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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/Linux-v5.15/Documentation/arm/omap/ |
D | dss.rst | 32 - Use DSI DPLL to create DSS FCK 301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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/Linux-v5.15/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
D | reg.h | 256 #define DPLL 0x034A macro
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/Linux-v5.15/Documentation/networking/device_drivers/hamradio/ |
D | z8530drv.rst | 308 present at all (BayCom). It feeds back the output of the DPLL
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/Linux-v5.15/drivers/gpu/drm/i915/ |
D | i915_reg.h | 3468 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro
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