Lines Matching refs:DPLL
1380 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1457 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1458 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1461 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1508 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1511 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1547 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
1567 intel_de_write(dev_priv, DPLL(pipe), in vlv_prepare_pll()
1668 intel_de_write(dev_priv, DPLL(pipe), in chv_prepare_pll()
1811 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_disable_pll()
1812 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
1828 intel_de_write(dev_priv, DPLL(pipe), val); in chv_disable_pll()
1829 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
1854 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1855 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()