Lines Matching refs:DPLL
474 val = intel_de_read(dev_priv, DPLL(pipe)); in assert_pll()
763 dpll_reg = DPLL(0); in vlv_wait_port_ready()
767 dpll_reg = DPLL(0); in vlv_wait_port_ready()
5199 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
5210 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
12682 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
12683 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
12686 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
12694 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
12698 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
12699 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
12736 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
12737 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_disable_pipe()