Searched refs:rd_reg_dword (Results 1 – 14 of 14) sorted by relevance
141 stat = rd_reg_dword(®->host_status); in qla27xx_dump_mpi_ram()152 rd_reg_dword(®->hccr); in qla27xx_dump_mpi_ram()159 rd_reg_dword(®->hccr); in qla27xx_dump_mpi_ram()218 stat = rd_reg_dword(®->host_status); in qla24xx_dump_ram()228 rd_reg_dword(®->hccr); in qla24xx_dump_ram()235 rd_reg_dword(®->hccr); in qla24xx_dump_ram()291 *buf++ = htonl(rd_reg_dword(dmp_reg)); in qla24xx_read_window()303 if (rd_reg_dword(®->host_status) & HSRX_RISC_PAUSED) in qla24xx_pause_risc()322 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_soft_reset()327 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_soft_reset()[all …]
685 rd_reg_dword(®->rsp_q_out); in qlafx00_config_rings()914 pseudo_aen = rd_reg_dword(®->pseudoaen); in qlafx00_init_fw_ready()916 aenmbx7 = rd_reg_dword(®->initval7); in qlafx00_init_fw_ready()927 aenmbx = rd_reg_dword(®->aenmailbox0); in qlafx00_init_fw_ready()946 aenmbx7 = rd_reg_dword(®->aenmailbox7); in qlafx00_init_fw_ready()949 ha->req_que_off = rd_reg_dword(®->aenmailbox1); in qlafx00_init_fw_ready()950 ha->rsp_que_off = rd_reg_dword(®->aenmailbox3); in qlafx00_init_fw_ready()951 ha->req_que_len = rd_reg_dword(®->aenmailbox5); in qlafx00_init_fw_ready()952 ha->rsp_que_len = rd_reg_dword(®->aenmailbox6); in qlafx00_init_fw_ready()984 aenmbx7 = rd_reg_dword(®->initval7); in qlafx00_init_fw_ready()[all …]
369 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)379 rd_reg_dword((ha)->cregbase + off)385 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)398 rd_reg_dword((ha)->cregbase + off)
461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) { in qla24xx_read_flash_dword()462 *data = rd_reg_dword(®->flash_data); in qla24xx_read_flash_dword()505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG)) in qla24xx_write_flash_dword()1202 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()1203 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()1245 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()1471 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1472 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()1495 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1496 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()[all …]
372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()481 data = rd_reg_dword(off); in qla82xx_rd_32()901 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_md_rw_32()908 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + in qla82xx_md_rw_32()2027 if (rd_reg_dword(®->host_int)) { in qla82xx_intr_handler()2028 stat = rd_reg_dword(®->host_status); in qla82xx_intr_handler()2093 host_int = rd_reg_dword(®->host_int); in qla82xx_msix_default()2097 stat = rd_reg_dword(®->host_status); in qla82xx_msix_default()2154 host_int = rd_reg_dword(®->host_int); in qla82xx_msix_rsp_q()2189 host_int = rd_reg_dword(®->host_int); in qla82xx_poll()[all …]
327 stat = rd_reg_dword(®->u.isp2300.host_status); in qla2300_intr_handler()3596 rd_reg_dword(®->iobase_addr); in qla2xxx_check_risc_status()3598 for (cnt = 10000; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3611 for (cnt = 100; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3623 if (rd_reg_dword(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()3629 rd_reg_dword(®->iobase_window); in qla2xxx_check_risc_status()3673 stat = rd_reg_dword(®->host_status); in qla24xx_intr_handler()3680 hccr = rd_reg_dword(®->hccr); in qla24xx_intr_handler()3802 stat = rd_reg_dword(®->host_status); in qla24xx_msix_default()3809 hccr = rd_reg_dword(®->hccr); in qla24xx_msix_default()
2495 ha->pci_attr = rd_reg_dword(®->ctrl_status); in qla24xx_pci_config()2754 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_reset_risc()2760 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_reset_risc()2765 rd_reg_dword(®->hccr), in qla24xx_reset_risc()2766 rd_reg_dword(®->ctrl_status), in qla24xx_reset_risc()2767 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)); in qla24xx_reset_risc()2791 rd_reg_dword(®->hccr), in qla24xx_reset_risc()2795 rd_reg_dword(®->ctrl_status); in qla24xx_reset_risc()2798 if ((rd_reg_dword(®->ctrl_status) & in qla24xx_reset_risc()2804 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) in qla24xx_reset_risc()[all …]
2298 cnt = rd_reg_dword(®->isp25mq.req_q_out); in __qla2x00_alloc_iocbs()2300 cnt = rd_reg_dword(reg->isp82.req_q_out); in __qla2x00_alloc_iocbs()2302 cnt = rd_reg_dword(®->isp24.req_q_out); in __qla2x00_alloc_iocbs()2304 cnt = rd_reg_dword(®->ispfx00.req_q_out); in __qla2x00_alloc_iocbs()3539 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_scsi()
302 if (rd_reg_dword(®->isp82.hint) & in qla2x00_mailbox_command()412 ictrl = rd_reg_dword(®->isp24.ictrl); in qla2x00_mailbox_command()413 host_status = rd_reg_dword(®->isp24.host_status); in qla2x00_mailbox_command()414 hccr = rd_reg_dword(®->isp24.hccr); in qla2x00_mailbox_command()567 rd_reg_dword(®->isp24.host_status), in qla2x00_mailbox_command()568 rd_reg_dword(®->isp24.ictrl), in qla2x00_mailbox_command()569 rd_reg_dword(®->isp24.istatus)); in qla2x00_mailbox_command()5440 stat = rd_reg_dword(®->host_status); in qla81xx_write_mpi_register()5451 rd_reg_dword(®->hccr); in qla81xx_write_mpi_register()
1228 return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT); in qla2x00_isp_reg_stat()1230 return ((rd_reg_dword(®->host_status)) == in qla2x00_isp_reg_stat()1943 rd_reg_dword(®->ictrl); in qla24xx_enable_intrs()1958 rd_reg_dword(®->ictrl); in qla24xx_disable_intrs()7502 stat = rd_reg_dword(®->u.isp2300.host_status); in qla2xxx_pci_mmio_enabled()7506 stat = rd_reg_dword(®24->host_status); in qla2xxx_pci_mmio_enabled()
72 value = rd_reg_dword(window); in qla27xx_read32()
3948 if (rd_reg_dword(®->host_int)) { in qla8044_intr_handler()3949 stat = rd_reg_dword(®->host_status); in qla8044_intr_handler()
142 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) in rd_reg_dword() function
6817 rd_reg_dword(ISP_ATIO_Q_OUT(vha)); in qlt_24xx_config_rings()
