2495 	ha->pci_attr = rd_reg_dword(&reg->ctrl_status);  in qla24xx_pci_config()
2754 		if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
2760 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
2765 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
2766 	    rd_reg_dword(&reg->ctrl_status),  in qla24xx_reset_risc()
2767 	    (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
2791 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
2795 	rd_reg_dword(&reg->ctrl_status);  in qla24xx_reset_risc()
2798 		if ((rd_reg_dword(&reg->ctrl_status) &  in qla24xx_reset_risc()
2804 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
2809 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
2810 	    rd_reg_dword(&reg->ctrl_status));  in qla24xx_reset_risc()
2830 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
2833 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
2836 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
2852 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
2873 	*data = rd_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);  in qla25xx_read_risc_sema_reg()
7160 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()
7162 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()