1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7 #include "qla_target.h"
8
9 #include <linux/delay.h>
10 #include <linux/gfp.h>
11
12 static struct mb_cmd_name {
13 uint16_t cmd;
14 const char *str;
15 } mb_str[] = {
16 {MBC_GET_PORT_DATABASE, "GPDB"},
17 {MBC_GET_ID_LIST, "GIDList"},
18 {MBC_GET_LINK_PRIV_STATS, "Stats"},
19 {MBC_GET_RESOURCE_COUNTS, "ResCnt"},
20 };
21
mb_to_str(uint16_t cmd)22 static const char *mb_to_str(uint16_t cmd)
23 {
24 int i;
25 struct mb_cmd_name *e;
26
27 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
28 e = mb_str + i;
29 if (cmd == e->cmd)
30 return e->str;
31 }
32 return "unknown";
33 }
34
35 static struct rom_cmd {
36 uint16_t cmd;
37 } rom_cmds[] = {
38 { MBC_LOAD_RAM },
39 { MBC_EXECUTE_FIRMWARE },
40 { MBC_READ_RAM_WORD },
41 { MBC_MAILBOX_REGISTER_TEST },
42 { MBC_VERIFY_CHECKSUM },
43 { MBC_GET_FIRMWARE_VERSION },
44 { MBC_LOAD_RISC_RAM },
45 { MBC_DUMP_RISC_RAM },
46 { MBC_LOAD_RISC_RAM_EXTENDED },
47 { MBC_DUMP_RISC_RAM_EXTENDED },
48 { MBC_WRITE_RAM_WORD_EXTENDED },
49 { MBC_READ_RAM_EXTENDED },
50 { MBC_GET_RESOURCE_COUNTS },
51 { MBC_SET_FIRMWARE_OPTION },
52 { MBC_MID_INITIALIZE_FIRMWARE },
53 { MBC_GET_FIRMWARE_STATE },
54 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
55 { MBC_GET_RETRY_COUNT },
56 { MBC_TRACE_CONTROL },
57 { MBC_INITIALIZE_MULTIQ },
58 { MBC_IOCB_COMMAND_A64 },
59 { MBC_GET_ADAPTER_LOOP_ID },
60 { MBC_READ_SFP },
61 { MBC_SET_RNID_PARAMS },
62 { MBC_GET_RNID_PARAMS },
63 { MBC_GET_SET_ZIO_THRESHOLD },
64 };
65
is_rom_cmd(uint16_t cmd)66 static int is_rom_cmd(uint16_t cmd)
67 {
68 int i;
69 struct rom_cmd *wc;
70
71 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
72 wc = rom_cmds + i;
73 if (wc->cmd == cmd)
74 return 1;
75 }
76
77 return 0;
78 }
79
80 /*
81 * qla2x00_mailbox_command
82 * Issue mailbox command and waits for completion.
83 *
84 * Input:
85 * ha = adapter block pointer.
86 * mcp = driver internal mbx struct pointer.
87 *
88 * Output:
89 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
90 *
91 * Returns:
92 * 0 : QLA_SUCCESS = cmd performed success
93 * 1 : QLA_FUNCTION_FAILED (error encountered)
94 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
95 *
96 * Context:
97 * Kernel context.
98 */
99 static int
qla2x00_mailbox_command(scsi_qla_host_t * vha,mbx_cmd_t * mcp)100 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
101 {
102 int rval, i;
103 unsigned long flags = 0;
104 device_reg_t *reg;
105 uint8_t abort_active;
106 uint8_t io_lock_on;
107 uint16_t command = 0;
108 uint16_t *iptr;
109 __le16 __iomem *optr;
110 uint32_t cnt;
111 uint32_t mboxes;
112 unsigned long wait_time;
113 struct qla_hw_data *ha = vha->hw;
114 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
115 u32 chip_reset;
116
117
118 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
119
120 if (ha->pdev->error_state == pci_channel_io_perm_failure) {
121 ql_log(ql_log_warn, vha, 0x1001,
122 "PCI channel failed permanently, exiting.\n");
123 return QLA_FUNCTION_TIMEOUT;
124 }
125
126 if (vha->device_flags & DFLG_DEV_FAILED) {
127 ql_log(ql_log_warn, vha, 0x1002,
128 "Device in failed state, exiting.\n");
129 return QLA_FUNCTION_TIMEOUT;
130 }
131
132 /* if PCI error, then avoid mbx processing.*/
133 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
134 test_bit(UNLOADING, &base_vha->dpc_flags)) {
135 ql_log(ql_log_warn, vha, 0xd04e,
136 "PCI error, exiting.\n");
137 return QLA_FUNCTION_TIMEOUT;
138 }
139
140 reg = ha->iobase;
141 io_lock_on = base_vha->flags.init_done;
142
143 rval = QLA_SUCCESS;
144 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
145 chip_reset = ha->chip_reset;
146
147 if (ha->flags.pci_channel_io_perm_failure) {
148 ql_log(ql_log_warn, vha, 0x1003,
149 "Perm failure on EEH timeout MBX, exiting.\n");
150 return QLA_FUNCTION_TIMEOUT;
151 }
152
153 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
154 /* Setting Link-Down error */
155 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
156 ql_log(ql_log_warn, vha, 0x1004,
157 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
158 return QLA_FUNCTION_TIMEOUT;
159 }
160
161 /* check if ISP abort is active and return cmd with timeout */
162 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
163 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
164 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
165 !is_rom_cmd(mcp->mb[0])) {
166 ql_log(ql_log_info, vha, 0x1005,
167 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
168 mcp->mb[0]);
169 return QLA_FUNCTION_TIMEOUT;
170 }
171
172 atomic_inc(&ha->num_pend_mbx_stage1);
173 /*
174 * Wait for active mailbox commands to finish by waiting at most tov
175 * seconds. This is to serialize actual issuing of mailbox cmds during
176 * non ISP abort time.
177 */
178 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
179 /* Timeout occurred. Return error. */
180 ql_log(ql_log_warn, vha, 0xd035,
181 "Cmd access timeout, cmd=0x%x, Exiting.\n",
182 mcp->mb[0]);
183 atomic_dec(&ha->num_pend_mbx_stage1);
184 return QLA_FUNCTION_TIMEOUT;
185 }
186 atomic_dec(&ha->num_pend_mbx_stage1);
187 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
188 rval = QLA_ABORTED;
189 goto premature_exit;
190 }
191
192
193 /* Save mailbox command for debug */
194 ha->mcp = mcp;
195
196 ql_dbg(ql_dbg_mbx, vha, 0x1006,
197 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
198
199 spin_lock_irqsave(&ha->hardware_lock, flags);
200
201 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset ||
202 ha->flags.mbox_busy) {
203 rval = QLA_ABORTED;
204 spin_unlock_irqrestore(&ha->hardware_lock, flags);
205 goto premature_exit;
206 }
207 ha->flags.mbox_busy = 1;
208
209 /* Load mailbox registers. */
210 if (IS_P3P_TYPE(ha))
211 optr = ®->isp82.mailbox_in[0];
212 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
213 optr = ®->isp24.mailbox0;
214 else
215 optr = MAILBOX_REG(ha, ®->isp, 0);
216
217 iptr = mcp->mb;
218 command = mcp->mb[0];
219 mboxes = mcp->out_mb;
220
221 ql_dbg(ql_dbg_mbx, vha, 0x1111,
222 "Mailbox registers (OUT):\n");
223 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
224 if (IS_QLA2200(ha) && cnt == 8)
225 optr = MAILBOX_REG(ha, ®->isp, 8);
226 if (mboxes & BIT_0) {
227 ql_dbg(ql_dbg_mbx, vha, 0x1112,
228 "mbox[%d]<-0x%04x\n", cnt, *iptr);
229 wrt_reg_word(optr, *iptr);
230 }
231
232 mboxes >>= 1;
233 optr++;
234 iptr++;
235 }
236
237 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
238 "I/O Address = %p.\n", optr);
239
240 /* Issue set host interrupt command to send cmd out. */
241 ha->flags.mbox_int = 0;
242 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
243
244 /* Unlock mbx registers and wait for interrupt */
245 ql_dbg(ql_dbg_mbx, vha, 0x100f,
246 "Going to unlock irq & waiting for interrupts. "
247 "jiffies=%lx.\n", jiffies);
248
249 /* Wait for mbx cmd completion until timeout */
250 atomic_inc(&ha->num_pend_mbx_stage2);
251 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
252 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
253
254 if (IS_P3P_TYPE(ha))
255 wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING);
256 else if (IS_FWI2_CAPABLE(ha))
257 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT);
258 else
259 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT);
260 spin_unlock_irqrestore(&ha->hardware_lock, flags);
261
262 wait_time = jiffies;
263 atomic_inc(&ha->num_pend_mbx_stage3);
264 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
265 mcp->tov * HZ)) {
266 if (chip_reset != ha->chip_reset) {
267 spin_lock_irqsave(&ha->hardware_lock, flags);
268 ha->flags.mbox_busy = 0;
269 spin_unlock_irqrestore(&ha->hardware_lock,
270 flags);
271 atomic_dec(&ha->num_pend_mbx_stage2);
272 atomic_dec(&ha->num_pend_mbx_stage3);
273 rval = QLA_ABORTED;
274 goto premature_exit;
275 }
276 ql_dbg(ql_dbg_mbx, vha, 0x117a,
277 "cmd=%x Timeout.\n", command);
278 spin_lock_irqsave(&ha->hardware_lock, flags);
279 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
280 spin_unlock_irqrestore(&ha->hardware_lock, flags);
281
282 } else if (ha->flags.purge_mbox ||
283 chip_reset != ha->chip_reset) {
284 spin_lock_irqsave(&ha->hardware_lock, flags);
285 ha->flags.mbox_busy = 0;
286 spin_unlock_irqrestore(&ha->hardware_lock, flags);
287 atomic_dec(&ha->num_pend_mbx_stage2);
288 atomic_dec(&ha->num_pend_mbx_stage3);
289 rval = QLA_ABORTED;
290 goto premature_exit;
291 }
292 atomic_dec(&ha->num_pend_mbx_stage3);
293
294 if (time_after(jiffies, wait_time + 5 * HZ))
295 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
296 command, jiffies_to_msecs(jiffies - wait_time));
297 } else {
298 ql_dbg(ql_dbg_mbx, vha, 0x1011,
299 "Cmd=%x Polling Mode.\n", command);
300
301 if (IS_P3P_TYPE(ha)) {
302 if (rd_reg_dword(®->isp82.hint) &
303 HINT_MBX_INT_PENDING) {
304 ha->flags.mbox_busy = 0;
305 spin_unlock_irqrestore(&ha->hardware_lock,
306 flags);
307 atomic_dec(&ha->num_pend_mbx_stage2);
308 ql_dbg(ql_dbg_mbx, vha, 0x1012,
309 "Pending mailbox timeout, exiting.\n");
310 rval = QLA_FUNCTION_TIMEOUT;
311 goto premature_exit;
312 }
313 wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING);
314 } else if (IS_FWI2_CAPABLE(ha))
315 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT);
316 else
317 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT);
318 spin_unlock_irqrestore(&ha->hardware_lock, flags);
319
320 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
321 while (!ha->flags.mbox_int) {
322 if (ha->flags.purge_mbox ||
323 chip_reset != ha->chip_reset) {
324 spin_lock_irqsave(&ha->hardware_lock, flags);
325 ha->flags.mbox_busy = 0;
326 spin_unlock_irqrestore(&ha->hardware_lock,
327 flags);
328 atomic_dec(&ha->num_pend_mbx_stage2);
329 rval = QLA_ABORTED;
330 goto premature_exit;
331 }
332
333 if (time_after(jiffies, wait_time))
334 break;
335
336 /* Check for pending interrupts. */
337 qla2x00_poll(ha->rsp_q_map[0]);
338
339 if (!ha->flags.mbox_int &&
340 !(IS_QLA2200(ha) &&
341 command == MBC_LOAD_RISC_RAM_EXTENDED))
342 msleep(10);
343 } /* while */
344 ql_dbg(ql_dbg_mbx, vha, 0x1013,
345 "Waited %d sec.\n",
346 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
347 }
348 atomic_dec(&ha->num_pend_mbx_stage2);
349
350 /* Check whether we timed out */
351 if (ha->flags.mbox_int) {
352 uint16_t *iptr2;
353
354 ql_dbg(ql_dbg_mbx, vha, 0x1014,
355 "Cmd=%x completed.\n", command);
356
357 /* Got interrupt. Clear the flag. */
358 ha->flags.mbox_int = 0;
359 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
360
361 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
362 spin_lock_irqsave(&ha->hardware_lock, flags);
363 ha->flags.mbox_busy = 0;
364 spin_unlock_irqrestore(&ha->hardware_lock, flags);
365
366 /* Setting Link-Down error */
367 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
368 ha->mcp = NULL;
369 rval = QLA_FUNCTION_FAILED;
370 ql_log(ql_log_warn, vha, 0xd048,
371 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
372 goto premature_exit;
373 }
374
375 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) {
376 ql_dbg(ql_dbg_mbx, vha, 0x11ff,
377 "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0],
378 MBS_COMMAND_COMPLETE);
379 rval = QLA_FUNCTION_FAILED;
380 }
381
382 /* Load return mailbox registers. */
383 iptr2 = mcp->mb;
384 iptr = (uint16_t *)&ha->mailbox_out[0];
385 mboxes = mcp->in_mb;
386
387 ql_dbg(ql_dbg_mbx, vha, 0x1113,
388 "Mailbox registers (IN):\n");
389 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
390 if (mboxes & BIT_0) {
391 *iptr2 = *iptr;
392 ql_dbg(ql_dbg_mbx, vha, 0x1114,
393 "mbox[%d]->0x%04x\n", cnt, *iptr2);
394 }
395
396 mboxes >>= 1;
397 iptr2++;
398 iptr++;
399 }
400 } else {
401
402 uint16_t mb[8];
403 uint32_t ictrl, host_status, hccr;
404 uint16_t w;
405
406 if (IS_FWI2_CAPABLE(ha)) {
407 mb[0] = rd_reg_word(®->isp24.mailbox0);
408 mb[1] = rd_reg_word(®->isp24.mailbox1);
409 mb[2] = rd_reg_word(®->isp24.mailbox2);
410 mb[3] = rd_reg_word(®->isp24.mailbox3);
411 mb[7] = rd_reg_word(®->isp24.mailbox7);
412 ictrl = rd_reg_dword(®->isp24.ictrl);
413 host_status = rd_reg_dword(®->isp24.host_status);
414 hccr = rd_reg_dword(®->isp24.hccr);
415
416 ql_log(ql_log_warn, vha, 0xd04c,
417 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
418 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
419 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
420 mb[7], host_status, hccr);
421
422 } else {
423 mb[0] = RD_MAILBOX_REG(ha, ®->isp, 0);
424 ictrl = rd_reg_word(®->isp.ictrl);
425 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
426 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
427 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
428 }
429 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
430
431 /* Capture FW dump only, if PCI device active */
432 if (!pci_channel_offline(vha->hw->pdev)) {
433 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
434 if (w == 0xffff || ictrl == 0xffffffff ||
435 (chip_reset != ha->chip_reset)) {
436 /* This is special case if there is unload
437 * of driver happening and if PCI device go
438 * into bad state due to PCI error condition
439 * then only PCI ERR flag would be set.
440 * we will do premature exit for above case.
441 */
442 spin_lock_irqsave(&ha->hardware_lock, flags);
443 ha->flags.mbox_busy = 0;
444 spin_unlock_irqrestore(&ha->hardware_lock,
445 flags);
446 rval = QLA_FUNCTION_TIMEOUT;
447 goto premature_exit;
448 }
449
450 /* Attempt to capture firmware dump for further
451 * anallysis of the current formware state. we do not
452 * need to do this if we are intentionally generating
453 * a dump
454 */
455 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
456 qla2xxx_dump_fw(vha);
457 rval = QLA_FUNCTION_TIMEOUT;
458 }
459 }
460 spin_lock_irqsave(&ha->hardware_lock, flags);
461 ha->flags.mbox_busy = 0;
462 spin_unlock_irqrestore(&ha->hardware_lock, flags);
463
464 /* Clean up */
465 ha->mcp = NULL;
466
467 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
468 ql_dbg(ql_dbg_mbx, vha, 0x101a,
469 "Checking for additional resp interrupt.\n");
470
471 /* polling mode for non isp_abort commands. */
472 qla2x00_poll(ha->rsp_q_map[0]);
473 }
474
475 if (rval == QLA_FUNCTION_TIMEOUT &&
476 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
477 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
478 ha->flags.eeh_busy) {
479 /* not in dpc. schedule it for dpc to take over. */
480 ql_dbg(ql_dbg_mbx, vha, 0x101b,
481 "Timeout, schedule isp_abort_needed.\n");
482
483 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
484 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
485 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
486 if (IS_QLA82XX(ha)) {
487 ql_dbg(ql_dbg_mbx, vha, 0x112a,
488 "disabling pause transmit on port "
489 "0 & 1.\n");
490 qla82xx_wr_32(ha,
491 QLA82XX_CRB_NIU + 0x98,
492 CRB_NIU_XG_PAUSE_CTL_P0|
493 CRB_NIU_XG_PAUSE_CTL_P1);
494 }
495 ql_log(ql_log_info, base_vha, 0x101c,
496 "Mailbox cmd timeout occurred, cmd=0x%x, "
497 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
498 "abort.\n", command, mcp->mb[0],
499 ha->flags.eeh_busy);
500 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
501 qla2xxx_wake_dpc(vha);
502 }
503 } else if (current == ha->dpc_thread) {
504 /* call abort directly since we are in the DPC thread */
505 ql_dbg(ql_dbg_mbx, vha, 0x101d,
506 "Timeout, calling abort_isp.\n");
507
508 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
509 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
510 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
511 if (IS_QLA82XX(ha)) {
512 ql_dbg(ql_dbg_mbx, vha, 0x112b,
513 "disabling pause transmit on port "
514 "0 & 1.\n");
515 qla82xx_wr_32(ha,
516 QLA82XX_CRB_NIU + 0x98,
517 CRB_NIU_XG_PAUSE_CTL_P0|
518 CRB_NIU_XG_PAUSE_CTL_P1);
519 }
520 ql_log(ql_log_info, base_vha, 0x101e,
521 "Mailbox cmd timeout occurred, cmd=0x%x, "
522 "mb[0]=0x%x. Scheduling ISP abort ",
523 command, mcp->mb[0]);
524 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
525 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
526 /* Allow next mbx cmd to come in. */
527 complete(&ha->mbx_cmd_comp);
528 if (ha->isp_ops->abort_isp(vha)) {
529 /* Failed. retry later. */
530 set_bit(ISP_ABORT_NEEDED,
531 &vha->dpc_flags);
532 }
533 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
534 ql_dbg(ql_dbg_mbx, vha, 0x101f,
535 "Finished abort_isp.\n");
536 goto mbx_done;
537 }
538 }
539 }
540
541 premature_exit:
542 /* Allow next mbx cmd to come in. */
543 complete(&ha->mbx_cmd_comp);
544
545 mbx_done:
546 if (rval == QLA_ABORTED) {
547 ql_log(ql_log_info, vha, 0xd035,
548 "Chip Reset in progress. Purging Mbox cmd=0x%x.\n",
549 mcp->mb[0]);
550 } else if (rval) {
551 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
552 pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR,
553 dev_name(&ha->pdev->dev), 0x1020+0x800,
554 vha->host_no, rval);
555 mboxes = mcp->in_mb;
556 cnt = 4;
557 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
558 if (mboxes & BIT_0) {
559 printk(" mb[%u]=%x", i, mcp->mb[i]);
560 cnt--;
561 }
562 pr_warn(" cmd=%x ****\n", command);
563 }
564 if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
565 ql_dbg(ql_dbg_mbx, vha, 0x1198,
566 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
567 rd_reg_dword(®->isp24.host_status),
568 rd_reg_dword(®->isp24.ictrl),
569 rd_reg_dword(®->isp24.istatus));
570 } else {
571 ql_dbg(ql_dbg_mbx, vha, 0x1206,
572 "ctrl_status=%#x ictrl=%#x istatus=%#x\n",
573 rd_reg_word(®->isp.ctrl_status),
574 rd_reg_word(®->isp.ictrl),
575 rd_reg_word(®->isp.istatus));
576 }
577 } else {
578 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
579 }
580
581 return rval;
582 }
583
584 int
qla2x00_load_ram(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t risc_addr,uint32_t risc_code_size)585 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
586 uint32_t risc_code_size)
587 {
588 int rval;
589 struct qla_hw_data *ha = vha->hw;
590 mbx_cmd_t mc;
591 mbx_cmd_t *mcp = &mc;
592
593 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
594 "Entered %s.\n", __func__);
595
596 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
597 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
598 mcp->mb[8] = MSW(risc_addr);
599 mcp->out_mb = MBX_8|MBX_0;
600 } else {
601 mcp->mb[0] = MBC_LOAD_RISC_RAM;
602 mcp->out_mb = MBX_0;
603 }
604 mcp->mb[1] = LSW(risc_addr);
605 mcp->mb[2] = MSW(req_dma);
606 mcp->mb[3] = LSW(req_dma);
607 mcp->mb[6] = MSW(MSD(req_dma));
608 mcp->mb[7] = LSW(MSD(req_dma));
609 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
610 if (IS_FWI2_CAPABLE(ha)) {
611 mcp->mb[4] = MSW(risc_code_size);
612 mcp->mb[5] = LSW(risc_code_size);
613 mcp->out_mb |= MBX_5|MBX_4;
614 } else {
615 mcp->mb[4] = LSW(risc_code_size);
616 mcp->out_mb |= MBX_4;
617 }
618
619 mcp->in_mb = MBX_1|MBX_0;
620 mcp->tov = MBX_TOV_SECONDS;
621 mcp->flags = 0;
622 rval = qla2x00_mailbox_command(vha, mcp);
623
624 if (rval != QLA_SUCCESS) {
625 ql_dbg(ql_dbg_mbx, vha, 0x1023,
626 "Failed=%x mb[0]=%x mb[1]=%x.\n",
627 rval, mcp->mb[0], mcp->mb[1]);
628 } else {
629 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
630 "Done %s.\n", __func__);
631 }
632
633 return rval;
634 }
635
636 #define NVME_ENABLE_FLAG BIT_3
637
638 /*
639 * qla2x00_execute_fw
640 * Start adapter firmware.
641 *
642 * Input:
643 * ha = adapter block pointer.
644 * TARGET_QUEUE_LOCK must be released.
645 * ADAPTER_STATE_LOCK must be released.
646 *
647 * Returns:
648 * qla2x00 local function return status code.
649 *
650 * Context:
651 * Kernel context.
652 */
653 int
qla2x00_execute_fw(scsi_qla_host_t * vha,uint32_t risc_addr)654 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
655 {
656 int rval;
657 struct qla_hw_data *ha = vha->hw;
658 mbx_cmd_t mc;
659 mbx_cmd_t *mcp = &mc;
660 u8 semaphore = 0;
661 #define EXE_FW_FORCE_SEMAPHORE BIT_7
662 u8 retry = 3;
663
664 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
665 "Entered %s.\n", __func__);
666
667 again:
668 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
669 mcp->out_mb = MBX_0;
670 mcp->in_mb = MBX_0;
671 if (IS_FWI2_CAPABLE(ha)) {
672 mcp->mb[1] = MSW(risc_addr);
673 mcp->mb[2] = LSW(risc_addr);
674 mcp->mb[3] = 0;
675 mcp->mb[4] = 0;
676 mcp->mb[11] = 0;
677
678 /* Enable BPM? */
679 if (ha->flags.lr_detected) {
680 mcp->mb[4] = BIT_0;
681 if (IS_BPM_RANGE_CAPABLE(ha))
682 mcp->mb[4] |=
683 ha->lr_distance << LR_DIST_FW_POS;
684 }
685
686 if (ql2xnvmeenable && (IS_QLA27XX(ha) || IS_QLA28XX(ha)))
687 mcp->mb[4] |= NVME_ENABLE_FLAG;
688
689 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
690 struct nvram_81xx *nv = ha->nvram;
691 /* set minimum speed if specified in nvram */
692 if (nv->min_supported_speed >= 2 &&
693 nv->min_supported_speed <= 5) {
694 mcp->mb[4] |= BIT_4;
695 mcp->mb[11] |= nv->min_supported_speed & 0xF;
696 mcp->out_mb |= MBX_11;
697 mcp->in_mb |= BIT_5;
698 vha->min_supported_speed =
699 nv->min_supported_speed;
700 }
701 }
702
703 if (ha->flags.exlogins_enabled)
704 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
705
706 if (ha->flags.exchoffld_enabled)
707 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
708
709 if (semaphore)
710 mcp->mb[11] |= EXE_FW_FORCE_SEMAPHORE;
711
712 mcp->out_mb |= MBX_4 | MBX_3 | MBX_2 | MBX_1 | MBX_11;
713 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1;
714 } else {
715 mcp->mb[1] = LSW(risc_addr);
716 mcp->out_mb |= MBX_1;
717 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
718 mcp->mb[2] = 0;
719 mcp->out_mb |= MBX_2;
720 }
721 }
722
723 mcp->tov = MBX_TOV_SECONDS;
724 mcp->flags = 0;
725 rval = qla2x00_mailbox_command(vha, mcp);
726
727 if (rval != QLA_SUCCESS) {
728 if (IS_QLA28XX(ha) && rval == QLA_COMMAND_ERROR &&
729 mcp->mb[1] == 0x27 && retry) {
730 semaphore = 1;
731 retry--;
732 ql_dbg(ql_dbg_async, vha, 0x1026,
733 "Exe FW: force semaphore.\n");
734 goto again;
735 }
736
737 ql_dbg(ql_dbg_mbx, vha, 0x1026,
738 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
739 return rval;
740 }
741
742 if (!IS_FWI2_CAPABLE(ha))
743 goto done;
744
745 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
746 ql_dbg(ql_dbg_mbx, vha, 0x119a,
747 "fw_ability_mask=%x.\n", ha->fw_ability_mask);
748 ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
749 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
750 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1);
751 ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
752 ha->max_supported_speed == 0 ? "16Gps" :
753 ha->max_supported_speed == 1 ? "32Gps" :
754 ha->max_supported_speed == 2 ? "64Gps" : "unknown");
755 if (vha->min_supported_speed) {
756 ha->min_supported_speed = mcp->mb[5] &
757 (BIT_0 | BIT_1 | BIT_2);
758 ql_dbg(ql_dbg_mbx, vha, 0x119c,
759 "min_supported_speed=%s.\n",
760 ha->min_supported_speed == 6 ? "64Gps" :
761 ha->min_supported_speed == 5 ? "32Gps" :
762 ha->min_supported_speed == 4 ? "16Gps" :
763 ha->min_supported_speed == 3 ? "8Gps" :
764 ha->min_supported_speed == 2 ? "4Gps" : "unknown");
765 }
766 }
767
768 done:
769 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
770 "Done %s.\n", __func__);
771
772 return rval;
773 }
774
775 /*
776 * qla_get_exlogin_status
777 * Get extended login status
778 * uses the memory offload control/status Mailbox
779 *
780 * Input:
781 * ha: adapter state pointer.
782 * fwopt: firmware options
783 *
784 * Returns:
785 * qla2x00 local function status
786 *
787 * Context:
788 * Kernel context.
789 */
790 #define FETCH_XLOGINS_STAT 0x8
791 int
qla_get_exlogin_status(scsi_qla_host_t * vha,uint16_t * buf_sz,uint16_t * ex_logins_cnt)792 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
793 uint16_t *ex_logins_cnt)
794 {
795 int rval;
796 mbx_cmd_t mc;
797 mbx_cmd_t *mcp = &mc;
798
799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
800 "Entered %s\n", __func__);
801
802 memset(mcp->mb, 0 , sizeof(mcp->mb));
803 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
804 mcp->mb[1] = FETCH_XLOGINS_STAT;
805 mcp->out_mb = MBX_1|MBX_0;
806 mcp->in_mb = MBX_10|MBX_4|MBX_0;
807 mcp->tov = MBX_TOV_SECONDS;
808 mcp->flags = 0;
809
810 rval = qla2x00_mailbox_command(vha, mcp);
811 if (rval != QLA_SUCCESS) {
812 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
813 } else {
814 *buf_sz = mcp->mb[4];
815 *ex_logins_cnt = mcp->mb[10];
816
817 ql_log(ql_log_info, vha, 0x1190,
818 "buffer size 0x%x, exchange login count=%d\n",
819 mcp->mb[4], mcp->mb[10]);
820
821 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
822 "Done %s.\n", __func__);
823 }
824
825 return rval;
826 }
827
828 /*
829 * qla_set_exlogin_mem_cfg
830 * set extended login memory configuration
831 * Mbx needs to be issues before init_cb is set
832 *
833 * Input:
834 * ha: adapter state pointer.
835 * buffer: buffer pointer
836 * phys_addr: physical address of buffer
837 * size: size of buffer
838 * TARGET_QUEUE_LOCK must be released
839 * ADAPTER_STATE_LOCK must be release
840 *
841 * Returns:
842 * qla2x00 local funxtion status code.
843 *
844 * Context:
845 * Kernel context.
846 */
847 #define CONFIG_XLOGINS_MEM 0x9
848 int
qla_set_exlogin_mem_cfg(scsi_qla_host_t * vha,dma_addr_t phys_addr)849 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
850 {
851 int rval;
852 mbx_cmd_t mc;
853 mbx_cmd_t *mcp = &mc;
854 struct qla_hw_data *ha = vha->hw;
855
856 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
857 "Entered %s.\n", __func__);
858
859 memset(mcp->mb, 0 , sizeof(mcp->mb));
860 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
861 mcp->mb[1] = CONFIG_XLOGINS_MEM;
862 mcp->mb[2] = MSW(phys_addr);
863 mcp->mb[3] = LSW(phys_addr);
864 mcp->mb[6] = MSW(MSD(phys_addr));
865 mcp->mb[7] = LSW(MSD(phys_addr));
866 mcp->mb[8] = MSW(ha->exlogin_size);
867 mcp->mb[9] = LSW(ha->exlogin_size);
868 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
869 mcp->in_mb = MBX_11|MBX_0;
870 mcp->tov = MBX_TOV_SECONDS;
871 mcp->flags = 0;
872 rval = qla2x00_mailbox_command(vha, mcp);
873 if (rval != QLA_SUCCESS) {
874 ql_dbg(ql_dbg_mbx, vha, 0x111b,
875 "EXlogin Failed=%x. MB0=%x MB11=%x\n",
876 rval, mcp->mb[0], mcp->mb[11]);
877 } else {
878 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
879 "Done %s.\n", __func__);
880 }
881
882 return rval;
883 }
884
885 /*
886 * qla_get_exchoffld_status
887 * Get exchange offload status
888 * uses the memory offload control/status Mailbox
889 *
890 * Input:
891 * ha: adapter state pointer.
892 * fwopt: firmware options
893 *
894 * Returns:
895 * qla2x00 local function status
896 *
897 * Context:
898 * Kernel context.
899 */
900 #define FETCH_XCHOFFLD_STAT 0x2
901 int
qla_get_exchoffld_status(scsi_qla_host_t * vha,uint16_t * buf_sz,uint16_t * ex_logins_cnt)902 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
903 uint16_t *ex_logins_cnt)
904 {
905 int rval;
906 mbx_cmd_t mc;
907 mbx_cmd_t *mcp = &mc;
908
909 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
910 "Entered %s\n", __func__);
911
912 memset(mcp->mb, 0 , sizeof(mcp->mb));
913 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
914 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
915 mcp->out_mb = MBX_1|MBX_0;
916 mcp->in_mb = MBX_10|MBX_4|MBX_0;
917 mcp->tov = MBX_TOV_SECONDS;
918 mcp->flags = 0;
919
920 rval = qla2x00_mailbox_command(vha, mcp);
921 if (rval != QLA_SUCCESS) {
922 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
923 } else {
924 *buf_sz = mcp->mb[4];
925 *ex_logins_cnt = mcp->mb[10];
926
927 ql_log(ql_log_info, vha, 0x118e,
928 "buffer size 0x%x, exchange offload count=%d\n",
929 mcp->mb[4], mcp->mb[10]);
930
931 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
932 "Done %s.\n", __func__);
933 }
934
935 return rval;
936 }
937
938 /*
939 * qla_set_exchoffld_mem_cfg
940 * Set exchange offload memory configuration
941 * Mbx needs to be issues before init_cb is set
942 *
943 * Input:
944 * ha: adapter state pointer.
945 * buffer: buffer pointer
946 * phys_addr: physical address of buffer
947 * size: size of buffer
948 * TARGET_QUEUE_LOCK must be released
949 * ADAPTER_STATE_LOCK must be release
950 *
951 * Returns:
952 * qla2x00 local funxtion status code.
953 *
954 * Context:
955 * Kernel context.
956 */
957 #define CONFIG_XCHOFFLD_MEM 0x3
958 int
qla_set_exchoffld_mem_cfg(scsi_qla_host_t * vha)959 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
960 {
961 int rval;
962 mbx_cmd_t mc;
963 mbx_cmd_t *mcp = &mc;
964 struct qla_hw_data *ha = vha->hw;
965
966 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
967 "Entered %s.\n", __func__);
968
969 memset(mcp->mb, 0 , sizeof(mcp->mb));
970 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
971 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
972 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
973 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
974 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
975 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
976 mcp->mb[8] = MSW(ha->exchoffld_size);
977 mcp->mb[9] = LSW(ha->exchoffld_size);
978 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
979 mcp->in_mb = MBX_11|MBX_0;
980 mcp->tov = MBX_TOV_SECONDS;
981 mcp->flags = 0;
982 rval = qla2x00_mailbox_command(vha, mcp);
983 if (rval != QLA_SUCCESS) {
984 /*EMPTY*/
985 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
986 } else {
987 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
988 "Done %s.\n", __func__);
989 }
990
991 return rval;
992 }
993
994 /*
995 * qla2x00_get_fw_version
996 * Get firmware version.
997 *
998 * Input:
999 * ha: adapter state pointer.
1000 * major: pointer for major number.
1001 * minor: pointer for minor number.
1002 * subminor: pointer for subminor number.
1003 *
1004 * Returns:
1005 * qla2x00 local function return status code.
1006 *
1007 * Context:
1008 * Kernel context.
1009 */
1010 int
qla2x00_get_fw_version(scsi_qla_host_t * vha)1011 qla2x00_get_fw_version(scsi_qla_host_t *vha)
1012 {
1013 int rval;
1014 mbx_cmd_t mc;
1015 mbx_cmd_t *mcp = &mc;
1016 struct qla_hw_data *ha = vha->hw;
1017
1018 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
1019 "Entered %s.\n", __func__);
1020
1021 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
1022 mcp->out_mb = MBX_0;
1023 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1024 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
1025 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
1026 if (IS_FWI2_CAPABLE(ha))
1027 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
1028 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
1029 mcp->in_mb |=
1030 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
1031 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7;
1032
1033 mcp->flags = 0;
1034 mcp->tov = MBX_TOV_SECONDS;
1035 rval = qla2x00_mailbox_command(vha, mcp);
1036 if (rval != QLA_SUCCESS)
1037 goto failed;
1038
1039 /* Return mailbox data. */
1040 ha->fw_major_version = mcp->mb[1];
1041 ha->fw_minor_version = mcp->mb[2];
1042 ha->fw_subminor_version = mcp->mb[3];
1043 ha->fw_attributes = mcp->mb[6];
1044 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
1045 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1046 else
1047 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
1048
1049 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
1050 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1051 ha->mpi_version[1] = mcp->mb[11] >> 8;
1052 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1053 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
1054 ha->phy_version[0] = mcp->mb[8] & 0xff;
1055 ha->phy_version[1] = mcp->mb[9] >> 8;
1056 ha->phy_version[2] = mcp->mb[9] & 0xff;
1057 }
1058
1059 if (IS_FWI2_CAPABLE(ha)) {
1060 ha->fw_attributes_h = mcp->mb[15];
1061 ha->fw_attributes_ext[0] = mcp->mb[16];
1062 ha->fw_attributes_ext[1] = mcp->mb[17];
1063 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
1064 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
1065 __func__, mcp->mb[15], mcp->mb[6]);
1066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
1067 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
1068 __func__, mcp->mb[17], mcp->mb[16]);
1069
1070 if (ha->fw_attributes_h & 0x4)
1071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
1072 "%s: Firmware supports Extended Login 0x%x\n",
1073 __func__, ha->fw_attributes_h);
1074
1075 if (ha->fw_attributes_h & 0x8)
1076 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
1077 "%s: Firmware supports Exchange Offload 0x%x\n",
1078 __func__, ha->fw_attributes_h);
1079
1080 /*
1081 * FW supports nvme and driver load parameter requested nvme.
1082 * BIT 26 of fw_attributes indicates NVMe support.
1083 */
1084 if ((ha->fw_attributes_h &
1085 (FW_ATTR_H_NVME | FW_ATTR_H_NVME_UPDATED)) &&
1086 ql2xnvmeenable) {
1087 if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST)
1088 vha->flags.nvme_first_burst = 1;
1089
1090 vha->flags.nvme_enabled = 1;
1091 ql_log(ql_log_info, vha, 0xd302,
1092 "%s: FC-NVMe is Enabled (0x%x)\n",
1093 __func__, ha->fw_attributes_h);
1094 }
1095
1096 /* BIT_13 of Extended FW Attributes informs about NVMe2 support */
1097 if (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_NVME2) {
1098 ql_log(ql_log_info, vha, 0xd302,
1099 "Firmware supports NVMe2 0x%x\n",
1100 ha->fw_attributes_ext[0]);
1101 vha->flags.nvme2_enabled = 1;
1102 }
1103 }
1104
1105 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
1106 ha->serdes_version[0] = mcp->mb[7] & 0xff;
1107 ha->serdes_version[1] = mcp->mb[8] >> 8;
1108 ha->serdes_version[2] = mcp->mb[8] & 0xff;
1109 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1110 ha->mpi_version[1] = mcp->mb[11] >> 8;
1111 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1112 ha->pep_version[0] = mcp->mb[13] & 0xff;
1113 ha->pep_version[1] = mcp->mb[14] >> 8;
1114 ha->pep_version[2] = mcp->mb[14] & 0xff;
1115 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
1116 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
1117 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
1118 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
1119 if (IS_QLA28XX(ha)) {
1120 if (mcp->mb[16] & BIT_10)
1121 ha->flags.secure_fw = 1;
1122
1123 ql_log(ql_log_info, vha, 0xffff,
1124 "Secure Flash Update in FW: %s\n",
1125 (ha->flags.secure_fw) ? "Supported" :
1126 "Not Supported");
1127 }
1128
1129 if (ha->flags.scm_supported_a &&
1130 (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) {
1131 ha->flags.scm_supported_f = 1;
1132 ha->sf_init_cb->flags |= BIT_13;
1133 }
1134 ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n",
1135 (ha->flags.scm_supported_f) ? "Supported" :
1136 "Not Supported");
1137
1138 if (vha->flags.nvme2_enabled) {
1139 /* set BIT_15 of special feature control block for SLER */
1140 ha->sf_init_cb->flags |= BIT_15;
1141 /* set BIT_14 of special feature control block for PI CTRL*/
1142 ha->sf_init_cb->flags |= BIT_14;
1143 }
1144 }
1145
1146 failed:
1147 if (rval != QLA_SUCCESS) {
1148 /*EMPTY*/
1149 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1150 } else {
1151 /*EMPTY*/
1152 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
1153 "Done %s.\n", __func__);
1154 }
1155 return rval;
1156 }
1157
1158 /*
1159 * qla2x00_get_fw_options
1160 * Set firmware options.
1161 *
1162 * Input:
1163 * ha = adapter block pointer.
1164 * fwopt = pointer for firmware options.
1165 *
1166 * Returns:
1167 * qla2x00 local function return status code.
1168 *
1169 * Context:
1170 * Kernel context.
1171 */
1172 int
qla2x00_get_fw_options(scsi_qla_host_t * vha,uint16_t * fwopts)1173 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1174 {
1175 int rval;
1176 mbx_cmd_t mc;
1177 mbx_cmd_t *mcp = &mc;
1178
1179 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
1180 "Entered %s.\n", __func__);
1181
1182 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
1183 mcp->out_mb = MBX_0;
1184 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1185 mcp->tov = MBX_TOV_SECONDS;
1186 mcp->flags = 0;
1187 rval = qla2x00_mailbox_command(vha, mcp);
1188
1189 if (rval != QLA_SUCCESS) {
1190 /*EMPTY*/
1191 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1192 } else {
1193 fwopts[0] = mcp->mb[0];
1194 fwopts[1] = mcp->mb[1];
1195 fwopts[2] = mcp->mb[2];
1196 fwopts[3] = mcp->mb[3];
1197
1198 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1199 "Done %s.\n", __func__);
1200 }
1201
1202 return rval;
1203 }
1204
1205
1206 /*
1207 * qla2x00_set_fw_options
1208 * Set firmware options.
1209 *
1210 * Input:
1211 * ha = adapter block pointer.
1212 * fwopt = pointer for firmware options.
1213 *
1214 * Returns:
1215 * qla2x00 local function return status code.
1216 *
1217 * Context:
1218 * Kernel context.
1219 */
1220 int
qla2x00_set_fw_options(scsi_qla_host_t * vha,uint16_t * fwopts)1221 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1222 {
1223 int rval;
1224 mbx_cmd_t mc;
1225 mbx_cmd_t *mcp = &mc;
1226
1227 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1228 "Entered %s.\n", __func__);
1229
1230 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1231 mcp->mb[1] = fwopts[1];
1232 mcp->mb[2] = fwopts[2];
1233 mcp->mb[3] = fwopts[3];
1234 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1235 mcp->in_mb = MBX_0;
1236 if (IS_FWI2_CAPABLE(vha->hw)) {
1237 mcp->in_mb |= MBX_1;
1238 mcp->mb[10] = fwopts[10];
1239 mcp->out_mb |= MBX_10;
1240 } else {
1241 mcp->mb[10] = fwopts[10];
1242 mcp->mb[11] = fwopts[11];
1243 mcp->mb[12] = 0; /* Undocumented, but used */
1244 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1245 }
1246 mcp->tov = MBX_TOV_SECONDS;
1247 mcp->flags = 0;
1248 rval = qla2x00_mailbox_command(vha, mcp);
1249
1250 fwopts[0] = mcp->mb[0];
1251
1252 if (rval != QLA_SUCCESS) {
1253 /*EMPTY*/
1254 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1255 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1256 } else {
1257 /*EMPTY*/
1258 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1259 "Done %s.\n", __func__);
1260 }
1261
1262 return rval;
1263 }
1264
1265 /*
1266 * qla2x00_mbx_reg_test
1267 * Mailbox register wrap test.
1268 *
1269 * Input:
1270 * ha = adapter block pointer.
1271 * TARGET_QUEUE_LOCK must be released.
1272 * ADAPTER_STATE_LOCK must be released.
1273 *
1274 * Returns:
1275 * qla2x00 local function return status code.
1276 *
1277 * Context:
1278 * Kernel context.
1279 */
1280 int
qla2x00_mbx_reg_test(scsi_qla_host_t * vha)1281 qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1282 {
1283 int rval;
1284 mbx_cmd_t mc;
1285 mbx_cmd_t *mcp = &mc;
1286
1287 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1288 "Entered %s.\n", __func__);
1289
1290 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1291 mcp->mb[1] = 0xAAAA;
1292 mcp->mb[2] = 0x5555;
1293 mcp->mb[3] = 0xAA55;
1294 mcp->mb[4] = 0x55AA;
1295 mcp->mb[5] = 0xA5A5;
1296 mcp->mb[6] = 0x5A5A;
1297 mcp->mb[7] = 0x2525;
1298 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1299 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1300 mcp->tov = MBX_TOV_SECONDS;
1301 mcp->flags = 0;
1302 rval = qla2x00_mailbox_command(vha, mcp);
1303
1304 if (rval == QLA_SUCCESS) {
1305 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1306 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1307 rval = QLA_FUNCTION_FAILED;
1308 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1309 mcp->mb[7] != 0x2525)
1310 rval = QLA_FUNCTION_FAILED;
1311 }
1312
1313 if (rval != QLA_SUCCESS) {
1314 /*EMPTY*/
1315 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1316 } else {
1317 /*EMPTY*/
1318 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1319 "Done %s.\n", __func__);
1320 }
1321
1322 return rval;
1323 }
1324
1325 /*
1326 * qla2x00_verify_checksum
1327 * Verify firmware checksum.
1328 *
1329 * Input:
1330 * ha = adapter block pointer.
1331 * TARGET_QUEUE_LOCK must be released.
1332 * ADAPTER_STATE_LOCK must be released.
1333 *
1334 * Returns:
1335 * qla2x00 local function return status code.
1336 *
1337 * Context:
1338 * Kernel context.
1339 */
1340 int
qla2x00_verify_checksum(scsi_qla_host_t * vha,uint32_t risc_addr)1341 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1342 {
1343 int rval;
1344 mbx_cmd_t mc;
1345 mbx_cmd_t *mcp = &mc;
1346
1347 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1348 "Entered %s.\n", __func__);
1349
1350 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1351 mcp->out_mb = MBX_0;
1352 mcp->in_mb = MBX_0;
1353 if (IS_FWI2_CAPABLE(vha->hw)) {
1354 mcp->mb[1] = MSW(risc_addr);
1355 mcp->mb[2] = LSW(risc_addr);
1356 mcp->out_mb |= MBX_2|MBX_1;
1357 mcp->in_mb |= MBX_2|MBX_1;
1358 } else {
1359 mcp->mb[1] = LSW(risc_addr);
1360 mcp->out_mb |= MBX_1;
1361 mcp->in_mb |= MBX_1;
1362 }
1363
1364 mcp->tov = MBX_TOV_SECONDS;
1365 mcp->flags = 0;
1366 rval = qla2x00_mailbox_command(vha, mcp);
1367
1368 if (rval != QLA_SUCCESS) {
1369 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1370 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1371 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1372 } else {
1373 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1374 "Done %s.\n", __func__);
1375 }
1376
1377 return rval;
1378 }
1379
1380 /*
1381 * qla2x00_issue_iocb
1382 * Issue IOCB using mailbox command
1383 *
1384 * Input:
1385 * ha = adapter state pointer.
1386 * buffer = buffer pointer.
1387 * phys_addr = physical address of buffer.
1388 * size = size of buffer.
1389 * TARGET_QUEUE_LOCK must be released.
1390 * ADAPTER_STATE_LOCK must be released.
1391 *
1392 * Returns:
1393 * qla2x00 local function return status code.
1394 *
1395 * Context:
1396 * Kernel context.
1397 */
1398 int
qla2x00_issue_iocb_timeout(scsi_qla_host_t * vha,void * buffer,dma_addr_t phys_addr,size_t size,uint32_t tov)1399 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
1400 dma_addr_t phys_addr, size_t size, uint32_t tov)
1401 {
1402 int rval;
1403 mbx_cmd_t mc;
1404 mbx_cmd_t *mcp = &mc;
1405
1406 if (!vha->hw->flags.fw_started)
1407 return QLA_INVALID_COMMAND;
1408
1409 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1410 "Entered %s.\n", __func__);
1411
1412 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1413 mcp->mb[1] = 0;
1414 mcp->mb[2] = MSW(LSD(phys_addr));
1415 mcp->mb[3] = LSW(LSD(phys_addr));
1416 mcp->mb[6] = MSW(MSD(phys_addr));
1417 mcp->mb[7] = LSW(MSD(phys_addr));
1418 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1419 mcp->in_mb = MBX_1|MBX_0;
1420 mcp->tov = tov;
1421 mcp->flags = 0;
1422 rval = qla2x00_mailbox_command(vha, mcp);
1423
1424 if (rval != QLA_SUCCESS) {
1425 /*EMPTY*/
1426 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1427 } else {
1428 sts_entry_t *sts_entry = buffer;
1429
1430 /* Mask reserved bits. */
1431 sts_entry->entry_status &=
1432 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
1433 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1434 "Done %s (status=%x).\n", __func__,
1435 sts_entry->entry_status);
1436 }
1437
1438 return rval;
1439 }
1440
1441 int
qla2x00_issue_iocb(scsi_qla_host_t * vha,void * buffer,dma_addr_t phys_addr,size_t size)1442 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
1443 size_t size)
1444 {
1445 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
1446 MBX_TOV_SECONDS);
1447 }
1448
1449 /*
1450 * qla2x00_abort_command
1451 * Abort command aborts a specified IOCB.
1452 *
1453 * Input:
1454 * ha = adapter block pointer.
1455 * sp = SB structure pointer.
1456 *
1457 * Returns:
1458 * qla2x00 local function return status code.
1459 *
1460 * Context:
1461 * Kernel context.
1462 */
1463 int
qla2x00_abort_command(srb_t * sp)1464 qla2x00_abort_command(srb_t *sp)
1465 {
1466 unsigned long flags = 0;
1467 int rval;
1468 uint32_t handle = 0;
1469 mbx_cmd_t mc;
1470 mbx_cmd_t *mcp = &mc;
1471 fc_port_t *fcport = sp->fcport;
1472 scsi_qla_host_t *vha = fcport->vha;
1473 struct qla_hw_data *ha = vha->hw;
1474 struct req_que *req;
1475 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1476
1477 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1478 "Entered %s.\n", __func__);
1479
1480 if (sp->qpair)
1481 req = sp->qpair->req;
1482 else
1483 req = vha->req;
1484
1485 spin_lock_irqsave(&ha->hardware_lock, flags);
1486 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1487 if (req->outstanding_cmds[handle] == sp)
1488 break;
1489 }
1490 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1491
1492 if (handle == req->num_outstanding_cmds) {
1493 /* command not found */
1494 return QLA_FUNCTION_FAILED;
1495 }
1496
1497 mcp->mb[0] = MBC_ABORT_COMMAND;
1498 if (HAS_EXTENDED_IDS(ha))
1499 mcp->mb[1] = fcport->loop_id;
1500 else
1501 mcp->mb[1] = fcport->loop_id << 8;
1502 mcp->mb[2] = (uint16_t)handle;
1503 mcp->mb[3] = (uint16_t)(handle >> 16);
1504 mcp->mb[6] = (uint16_t)cmd->device->lun;
1505 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1506 mcp->in_mb = MBX_0;
1507 mcp->tov = MBX_TOV_SECONDS;
1508 mcp->flags = 0;
1509 rval = qla2x00_mailbox_command(vha, mcp);
1510
1511 if (rval != QLA_SUCCESS) {
1512 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1513 } else {
1514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1515 "Done %s.\n", __func__);
1516 }
1517
1518 return rval;
1519 }
1520
1521 int
qla2x00_abort_target(struct fc_port * fcport,uint64_t l,int tag)1522 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1523 {
1524 int rval, rval2;
1525 mbx_cmd_t mc;
1526 mbx_cmd_t *mcp = &mc;
1527 scsi_qla_host_t *vha;
1528
1529 vha = fcport->vha;
1530
1531 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1532 "Entered %s.\n", __func__);
1533
1534 mcp->mb[0] = MBC_ABORT_TARGET;
1535 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
1536 if (HAS_EXTENDED_IDS(vha->hw)) {
1537 mcp->mb[1] = fcport->loop_id;
1538 mcp->mb[10] = 0;
1539 mcp->out_mb |= MBX_10;
1540 } else {
1541 mcp->mb[1] = fcport->loop_id << 8;
1542 }
1543 mcp->mb[2] = vha->hw->loop_reset_delay;
1544 mcp->mb[9] = vha->vp_idx;
1545
1546 mcp->in_mb = MBX_0;
1547 mcp->tov = MBX_TOV_SECONDS;
1548 mcp->flags = 0;
1549 rval = qla2x00_mailbox_command(vha, mcp);
1550 if (rval != QLA_SUCCESS) {
1551 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1552 "Failed=%x.\n", rval);
1553 }
1554
1555 /* Issue marker IOCB. */
1556 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0,
1557 MK_SYNC_ID);
1558 if (rval2 != QLA_SUCCESS) {
1559 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1560 "Failed to issue marker IOCB (%x).\n", rval2);
1561 } else {
1562 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1563 "Done %s.\n", __func__);
1564 }
1565
1566 return rval;
1567 }
1568
1569 int
qla2x00_lun_reset(struct fc_port * fcport,uint64_t l,int tag)1570 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
1571 {
1572 int rval, rval2;
1573 mbx_cmd_t mc;
1574 mbx_cmd_t *mcp = &mc;
1575 scsi_qla_host_t *vha;
1576
1577 vha = fcport->vha;
1578
1579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1580 "Entered %s.\n", __func__);
1581
1582 mcp->mb[0] = MBC_LUN_RESET;
1583 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
1584 if (HAS_EXTENDED_IDS(vha->hw))
1585 mcp->mb[1] = fcport->loop_id;
1586 else
1587 mcp->mb[1] = fcport->loop_id << 8;
1588 mcp->mb[2] = (u32)l;
1589 mcp->mb[3] = 0;
1590 mcp->mb[9] = vha->vp_idx;
1591
1592 mcp->in_mb = MBX_0;
1593 mcp->tov = MBX_TOV_SECONDS;
1594 mcp->flags = 0;
1595 rval = qla2x00_mailbox_command(vha, mcp);
1596 if (rval != QLA_SUCCESS) {
1597 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
1598 }
1599
1600 /* Issue marker IOCB. */
1601 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l,
1602 MK_SYNC_ID_LUN);
1603 if (rval2 != QLA_SUCCESS) {
1604 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1605 "Failed to issue marker IOCB (%x).\n", rval2);
1606 } else {
1607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1608 "Done %s.\n", __func__);
1609 }
1610
1611 return rval;
1612 }
1613
1614 /*
1615 * qla2x00_get_adapter_id
1616 * Get adapter ID and topology.
1617 *
1618 * Input:
1619 * ha = adapter block pointer.
1620 * id = pointer for loop ID.
1621 * al_pa = pointer for AL_PA.
1622 * area = pointer for area.
1623 * domain = pointer for domain.
1624 * top = pointer for topology.
1625 * TARGET_QUEUE_LOCK must be released.
1626 * ADAPTER_STATE_LOCK must be released.
1627 *
1628 * Returns:
1629 * qla2x00 local function return status code.
1630 *
1631 * Context:
1632 * Kernel context.
1633 */
1634 int
qla2x00_get_adapter_id(scsi_qla_host_t * vha,uint16_t * id,uint8_t * al_pa,uint8_t * area,uint8_t * domain,uint16_t * top,uint16_t * sw_cap)1635 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1636 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1637 {
1638 int rval;
1639 mbx_cmd_t mc;
1640 mbx_cmd_t *mcp = &mc;
1641
1642 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1643 "Entered %s.\n", __func__);
1644
1645 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
1646 mcp->mb[9] = vha->vp_idx;
1647 mcp->out_mb = MBX_9|MBX_0;
1648 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1649 if (IS_CNA_CAPABLE(vha->hw))
1650 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1651 if (IS_FWI2_CAPABLE(vha->hw))
1652 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
1653 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) {
1654 mcp->in_mb |= MBX_15;
1655 mcp->out_mb |= MBX_7|MBX_21|MBX_22|MBX_23;
1656 }
1657
1658 mcp->tov = MBX_TOV_SECONDS;
1659 mcp->flags = 0;
1660 rval = qla2x00_mailbox_command(vha, mcp);
1661 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1662 rval = QLA_COMMAND_ERROR;
1663 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1664 rval = QLA_INVALID_COMMAND;
1665
1666 /* Return data. */
1667 *id = mcp->mb[1];
1668 *al_pa = LSB(mcp->mb[2]);
1669 *area = MSB(mcp->mb[2]);
1670 *domain = LSB(mcp->mb[3]);
1671 *top = mcp->mb[6];
1672 *sw_cap = mcp->mb[7];
1673
1674 if (rval != QLA_SUCCESS) {
1675 /*EMPTY*/
1676 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1677 } else {
1678 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1679 "Done %s.\n", __func__);
1680
1681 if (IS_CNA_CAPABLE(vha->hw)) {
1682 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1683 vha->fcoe_fcf_idx = mcp->mb[10];
1684 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1685 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1686 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1687 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1688 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1689 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1690 }
1691 /* If FA-WWN supported */
1692 if (IS_FAWWN_CAPABLE(vha->hw)) {
1693 if (mcp->mb[7] & BIT_14) {
1694 vha->port_name[0] = MSB(mcp->mb[16]);
1695 vha->port_name[1] = LSB(mcp->mb[16]);
1696 vha->port_name[2] = MSB(mcp->mb[17]);
1697 vha->port_name[3] = LSB(mcp->mb[17]);
1698 vha->port_name[4] = MSB(mcp->mb[18]);
1699 vha->port_name[5] = LSB(mcp->mb[18]);
1700 vha->port_name[6] = MSB(mcp->mb[19]);
1701 vha->port_name[7] = LSB(mcp->mb[19]);
1702 fc_host_port_name(vha->host) =
1703 wwn_to_u64(vha->port_name);
1704 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1705 "FA-WWN acquired %016llx\n",
1706 wwn_to_u64(vha->port_name));
1707 }
1708 }
1709
1710 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) {
1711 vha->bbcr = mcp->mb[15];
1712 if (mcp->mb[7] & SCM_EDC_ACC_RECEIVED) {
1713 ql_log(ql_log_info, vha, 0x11a4,
1714 "SCM: EDC ELS completed, flags 0x%x\n",
1715 mcp->mb[21]);
1716 }
1717 if (mcp->mb[7] & SCM_RDF_ACC_RECEIVED) {
1718 vha->hw->flags.scm_enabled = 1;
1719 vha->scm_fabric_connection_flags |=
1720 SCM_FLAG_RDF_COMPLETED;
1721 ql_log(ql_log_info, vha, 0x11a5,
1722 "SCM: RDF ELS completed, flags 0x%x\n",
1723 mcp->mb[23]);
1724 }
1725 }
1726 }
1727
1728 return rval;
1729 }
1730
1731 /*
1732 * qla2x00_get_retry_cnt
1733 * Get current firmware login retry count and delay.
1734 *
1735 * Input:
1736 * ha = adapter block pointer.
1737 * retry_cnt = pointer to login retry count.
1738 * tov = pointer to login timeout value.
1739 *
1740 * Returns:
1741 * qla2x00 local function return status code.
1742 *
1743 * Context:
1744 * Kernel context.
1745 */
1746 int
qla2x00_get_retry_cnt(scsi_qla_host_t * vha,uint8_t * retry_cnt,uint8_t * tov,uint16_t * r_a_tov)1747 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1748 uint16_t *r_a_tov)
1749 {
1750 int rval;
1751 uint16_t ratov;
1752 mbx_cmd_t mc;
1753 mbx_cmd_t *mcp = &mc;
1754
1755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1756 "Entered %s.\n", __func__);
1757
1758 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1759 mcp->out_mb = MBX_0;
1760 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1761 mcp->tov = MBX_TOV_SECONDS;
1762 mcp->flags = 0;
1763 rval = qla2x00_mailbox_command(vha, mcp);
1764
1765 if (rval != QLA_SUCCESS) {
1766 /*EMPTY*/
1767 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1768 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1769 } else {
1770 /* Convert returned data and check our values. */
1771 *r_a_tov = mcp->mb[3] / 2;
1772 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1773 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1774 /* Update to the larger values */
1775 *retry_cnt = (uint8_t)mcp->mb[1];
1776 *tov = ratov;
1777 }
1778
1779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
1780 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1781 }
1782
1783 return rval;
1784 }
1785
1786 /*
1787 * qla2x00_init_firmware
1788 * Initialize adapter firmware.
1789 *
1790 * Input:
1791 * ha = adapter block pointer.
1792 * dptr = Initialization control block pointer.
1793 * size = size of initialization control block.
1794 * TARGET_QUEUE_LOCK must be released.
1795 * ADAPTER_STATE_LOCK must be released.
1796 *
1797 * Returns:
1798 * qla2x00 local function return status code.
1799 *
1800 * Context:
1801 * Kernel context.
1802 */
1803 int
qla2x00_init_firmware(scsi_qla_host_t * vha,uint16_t size)1804 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1805 {
1806 int rval;
1807 mbx_cmd_t mc;
1808 mbx_cmd_t *mcp = &mc;
1809 struct qla_hw_data *ha = vha->hw;
1810
1811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1812 "Entered %s.\n", __func__);
1813
1814 if (IS_P3P_TYPE(ha) && ql2xdbwr)
1815 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
1816 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1817
1818 if (ha->flags.npiv_supported)
1819 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1820 else
1821 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1822
1823 mcp->mb[1] = 0;
1824 mcp->mb[2] = MSW(ha->init_cb_dma);
1825 mcp->mb[3] = LSW(ha->init_cb_dma);
1826 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1827 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1828 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1829 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1830 mcp->mb[1] = BIT_0;
1831 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1832 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1833 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1834 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1835 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1836 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1837 }
1838
1839 if (ha->flags.scm_supported_f || vha->flags.nvme2_enabled) {
1840 mcp->mb[1] |= BIT_1;
1841 mcp->mb[16] = MSW(ha->sf_init_cb_dma);
1842 mcp->mb[17] = LSW(ha->sf_init_cb_dma);
1843 mcp->mb[18] = MSW(MSD(ha->sf_init_cb_dma));
1844 mcp->mb[19] = LSW(MSD(ha->sf_init_cb_dma));
1845 mcp->mb[15] = sizeof(*ha->sf_init_cb);
1846 mcp->out_mb |= MBX_19|MBX_18|MBX_17|MBX_16|MBX_15;
1847 }
1848
1849 /* 1 and 2 should normally be captured. */
1850 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1851 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
1852 /* mb3 is additional info about the installed SFP. */
1853 mcp->in_mb |= MBX_3;
1854 mcp->buf_size = size;
1855 mcp->flags = MBX_DMA_OUT;
1856 mcp->tov = MBX_TOV_SECONDS;
1857 rval = qla2x00_mailbox_command(vha, mcp);
1858
1859 if (rval != QLA_SUCCESS) {
1860 /*EMPTY*/
1861 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1862 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
1863 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1864 if (ha->init_cb) {
1865 ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
1866 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1867 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
1868 }
1869 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1870 ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
1871 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
1872 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
1873 }
1874 } else {
1875 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
1876 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
1877 ql_dbg(ql_dbg_mbx, vha, 0x119d,
1878 "Invalid SFP/Validation Failed\n");
1879 }
1880 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1881 "Done %s.\n", __func__);
1882 }
1883
1884 return rval;
1885 }
1886
1887
1888 /*
1889 * qla2x00_get_port_database
1890 * Issue normal/enhanced get port database mailbox command
1891 * and copy device name as necessary.
1892 *
1893 * Input:
1894 * ha = adapter state pointer.
1895 * dev = structure pointer.
1896 * opt = enhanced cmd option byte.
1897 *
1898 * Returns:
1899 * qla2x00 local function return status code.
1900 *
1901 * Context:
1902 * Kernel context.
1903 */
1904 int
qla2x00_get_port_database(scsi_qla_host_t * vha,fc_port_t * fcport,uint8_t opt)1905 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1906 {
1907 int rval;
1908 mbx_cmd_t mc;
1909 mbx_cmd_t *mcp = &mc;
1910 port_database_t *pd;
1911 struct port_database_24xx *pd24;
1912 dma_addr_t pd_dma;
1913 struct qla_hw_data *ha = vha->hw;
1914
1915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1916 "Entered %s.\n", __func__);
1917
1918 pd24 = NULL;
1919 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1920 if (pd == NULL) {
1921 ql_log(ql_log_warn, vha, 0x1050,
1922 "Failed to allocate port database structure.\n");
1923 fcport->query = 0;
1924 return QLA_MEMORY_ALLOC_FAILED;
1925 }
1926
1927 mcp->mb[0] = MBC_GET_PORT_DATABASE;
1928 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1929 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1930 mcp->mb[2] = MSW(pd_dma);
1931 mcp->mb[3] = LSW(pd_dma);
1932 mcp->mb[6] = MSW(MSD(pd_dma));
1933 mcp->mb[7] = LSW(MSD(pd_dma));
1934 mcp->mb[9] = vha->vp_idx;
1935 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1936 mcp->in_mb = MBX_0;
1937 if (IS_FWI2_CAPABLE(ha)) {
1938 mcp->mb[1] = fcport->loop_id;
1939 mcp->mb[10] = opt;
1940 mcp->out_mb |= MBX_10|MBX_1;
1941 mcp->in_mb |= MBX_1;
1942 } else if (HAS_EXTENDED_IDS(ha)) {
1943 mcp->mb[1] = fcport->loop_id;
1944 mcp->mb[10] = opt;
1945 mcp->out_mb |= MBX_10|MBX_1;
1946 } else {
1947 mcp->mb[1] = fcport->loop_id << 8 | opt;
1948 mcp->out_mb |= MBX_1;
1949 }
1950 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1951 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1952 mcp->flags = MBX_DMA_IN;
1953 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1954 rval = qla2x00_mailbox_command(vha, mcp);
1955 if (rval != QLA_SUCCESS)
1956 goto gpd_error_out;
1957
1958 if (IS_FWI2_CAPABLE(ha)) {
1959 uint64_t zero = 0;
1960 u8 current_login_state, last_login_state;
1961
1962 pd24 = (struct port_database_24xx *) pd;
1963
1964 /* Check for logged in state. */
1965 if (NVME_TARGET(ha, fcport)) {
1966 current_login_state = pd24->current_login_state >> 4;
1967 last_login_state = pd24->last_login_state >> 4;
1968 } else {
1969 current_login_state = pd24->current_login_state & 0xf;
1970 last_login_state = pd24->last_login_state & 0xf;
1971 }
1972 fcport->current_login_state = pd24->current_login_state;
1973 fcport->last_login_state = pd24->last_login_state;
1974
1975 /* Check for logged in state. */
1976 if (current_login_state != PDS_PRLI_COMPLETE &&
1977 last_login_state != PDS_PRLI_COMPLETE) {
1978 ql_dbg(ql_dbg_mbx, vha, 0x119a,
1979 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
1980 current_login_state, last_login_state,
1981 fcport->loop_id);
1982 rval = QLA_FUNCTION_FAILED;
1983
1984 if (!fcport->query)
1985 goto gpd_error_out;
1986 }
1987
1988 if (fcport->loop_id == FC_NO_LOOP_ID ||
1989 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1990 memcmp(fcport->port_name, pd24->port_name, 8))) {
1991 /* We lost the device mid way. */
1992 rval = QLA_NOT_LOGGED_IN;
1993 goto gpd_error_out;
1994 }
1995
1996 /* Names are little-endian. */
1997 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1998 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1999
2000 /* Get port_id of device. */
2001 fcport->d_id.b.domain = pd24->port_id[0];
2002 fcport->d_id.b.area = pd24->port_id[1];
2003 fcport->d_id.b.al_pa = pd24->port_id[2];
2004 fcport->d_id.b.rsvd_1 = 0;
2005
2006 /* If not target must be initiator or unknown type. */
2007 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
2008 fcport->port_type = FCT_INITIATOR;
2009 else
2010 fcport->port_type = FCT_TARGET;
2011
2012 /* Passback COS information. */
2013 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
2014 FC_COS_CLASS2 : FC_COS_CLASS3;
2015
2016 if (pd24->prli_svc_param_word_3[0] & BIT_7)
2017 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
2018 } else {
2019 uint64_t zero = 0;
2020
2021 /* Check for logged in state. */
2022 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
2023 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
2024 ql_dbg(ql_dbg_mbx, vha, 0x100a,
2025 "Unable to verify login-state (%x/%x) - "
2026 "portid=%02x%02x%02x.\n", pd->master_state,
2027 pd->slave_state, fcport->d_id.b.domain,
2028 fcport->d_id.b.area, fcport->d_id.b.al_pa);
2029 rval = QLA_FUNCTION_FAILED;
2030 goto gpd_error_out;
2031 }
2032
2033 if (fcport->loop_id == FC_NO_LOOP_ID ||
2034 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
2035 memcmp(fcport->port_name, pd->port_name, 8))) {
2036 /* We lost the device mid way. */
2037 rval = QLA_NOT_LOGGED_IN;
2038 goto gpd_error_out;
2039 }
2040
2041 /* Names are little-endian. */
2042 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
2043 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
2044
2045 /* Get port_id of device. */
2046 fcport->d_id.b.domain = pd->port_id[0];
2047 fcport->d_id.b.area = pd->port_id[3];
2048 fcport->d_id.b.al_pa = pd->port_id[2];
2049 fcport->d_id.b.rsvd_1 = 0;
2050
2051 /* If not target must be initiator or unknown type. */
2052 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
2053 fcport->port_type = FCT_INITIATOR;
2054 else
2055 fcport->port_type = FCT_TARGET;
2056
2057 /* Passback COS information. */
2058 fcport->supported_classes = (pd->options & BIT_4) ?
2059 FC_COS_CLASS2 : FC_COS_CLASS3;
2060 }
2061
2062 gpd_error_out:
2063 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
2064 fcport->query = 0;
2065
2066 if (rval != QLA_SUCCESS) {
2067 ql_dbg(ql_dbg_mbx, vha, 0x1052,
2068 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
2069 mcp->mb[0], mcp->mb[1]);
2070 } else {
2071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
2072 "Done %s.\n", __func__);
2073 }
2074
2075 return rval;
2076 }
2077
2078 int
qla24xx_get_port_database(scsi_qla_host_t * vha,u16 nport_handle,struct port_database_24xx * pdb)2079 qla24xx_get_port_database(scsi_qla_host_t *vha, u16 nport_handle,
2080 struct port_database_24xx *pdb)
2081 {
2082 mbx_cmd_t mc;
2083 mbx_cmd_t *mcp = &mc;
2084 dma_addr_t pdb_dma;
2085 int rval;
2086
2087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1115,
2088 "Entered %s.\n", __func__);
2089
2090 memset(pdb, 0, sizeof(*pdb));
2091
2092 pdb_dma = dma_map_single(&vha->hw->pdev->dev, pdb,
2093 sizeof(*pdb), DMA_FROM_DEVICE);
2094 if (!pdb_dma) {
2095 ql_log(ql_log_warn, vha, 0x1116, "Failed to map dma buffer.\n");
2096 return QLA_MEMORY_ALLOC_FAILED;
2097 }
2098
2099 mcp->mb[0] = MBC_GET_PORT_DATABASE;
2100 mcp->mb[1] = nport_handle;
2101 mcp->mb[2] = MSW(LSD(pdb_dma));
2102 mcp->mb[3] = LSW(LSD(pdb_dma));
2103 mcp->mb[6] = MSW(MSD(pdb_dma));
2104 mcp->mb[7] = LSW(MSD(pdb_dma));
2105 mcp->mb[9] = 0;
2106 mcp->mb[10] = 0;
2107 mcp->out_mb = MBX_10|MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2108 mcp->in_mb = MBX_1|MBX_0;
2109 mcp->buf_size = sizeof(*pdb);
2110 mcp->flags = MBX_DMA_IN;
2111 mcp->tov = vha->hw->login_timeout * 2;
2112 rval = qla2x00_mailbox_command(vha, mcp);
2113
2114 if (rval != QLA_SUCCESS) {
2115 ql_dbg(ql_dbg_mbx, vha, 0x111a,
2116 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2117 rval, mcp->mb[0], mcp->mb[1]);
2118 } else {
2119 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111b,
2120 "Done %s.\n", __func__);
2121 }
2122
2123 dma_unmap_single(&vha->hw->pdev->dev, pdb_dma,
2124 sizeof(*pdb), DMA_FROM_DEVICE);
2125
2126 return rval;
2127 }
2128
2129 /*
2130 * qla2x00_get_firmware_state
2131 * Get adapter firmware state.
2132 *
2133 * Input:
2134 * ha = adapter block pointer.
2135 * dptr = pointer for firmware state.
2136 * TARGET_QUEUE_LOCK must be released.
2137 * ADAPTER_STATE_LOCK must be released.
2138 *
2139 * Returns:
2140 * qla2x00 local function return status code.
2141 *
2142 * Context:
2143 * Kernel context.
2144 */
2145 int
qla2x00_get_firmware_state(scsi_qla_host_t * vha,uint16_t * states)2146 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
2147 {
2148 int rval;
2149 mbx_cmd_t mc;
2150 mbx_cmd_t *mcp = &mc;
2151 struct qla_hw_data *ha = vha->hw;
2152
2153 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
2154 "Entered %s.\n", __func__);
2155
2156 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
2157 mcp->out_mb = MBX_0;
2158 if (IS_FWI2_CAPABLE(vha->hw))
2159 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2160 else
2161 mcp->in_mb = MBX_1|MBX_0;
2162 mcp->tov = MBX_TOV_SECONDS;
2163 mcp->flags = 0;
2164 rval = qla2x00_mailbox_command(vha, mcp);
2165
2166 /* Return firmware states. */
2167 states[0] = mcp->mb[1];
2168 if (IS_FWI2_CAPABLE(vha->hw)) {
2169 states[1] = mcp->mb[2];
2170 states[2] = mcp->mb[3]; /* SFP info */
2171 states[3] = mcp->mb[4];
2172 states[4] = mcp->mb[5];
2173 states[5] = mcp->mb[6]; /* DPORT status */
2174 }
2175
2176 if (rval != QLA_SUCCESS) {
2177 /*EMPTY*/
2178 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
2179 } else {
2180 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
2181 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
2182 ql_dbg(ql_dbg_mbx, vha, 0x119e,
2183 "Invalid SFP/Validation Failed\n");
2184 }
2185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
2186 "Done %s.\n", __func__);
2187 }
2188
2189 return rval;
2190 }
2191
2192 /*
2193 * qla2x00_get_port_name
2194 * Issue get port name mailbox command.
2195 * Returned name is in big endian format.
2196 *
2197 * Input:
2198 * ha = adapter block pointer.
2199 * loop_id = loop ID of device.
2200 * name = pointer for name.
2201 * TARGET_QUEUE_LOCK must be released.
2202 * ADAPTER_STATE_LOCK must be released.
2203 *
2204 * Returns:
2205 * qla2x00 local function return status code.
2206 *
2207 * Context:
2208 * Kernel context.
2209 */
2210 int
qla2x00_get_port_name(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t * name,uint8_t opt)2211 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
2212 uint8_t opt)
2213 {
2214 int rval;
2215 mbx_cmd_t mc;
2216 mbx_cmd_t *mcp = &mc;
2217
2218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
2219 "Entered %s.\n", __func__);
2220
2221 mcp->mb[0] = MBC_GET_PORT_NAME;
2222 mcp->mb[9] = vha->vp_idx;
2223 mcp->out_mb = MBX_9|MBX_1|MBX_0;
2224 if (HAS_EXTENDED_IDS(vha->hw)) {
2225 mcp->mb[1] = loop_id;
2226 mcp->mb[10] = opt;
2227 mcp->out_mb |= MBX_10;
2228 } else {
2229 mcp->mb[1] = loop_id << 8 | opt;
2230 }
2231
2232 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2233 mcp->tov = MBX_TOV_SECONDS;
2234 mcp->flags = 0;
2235 rval = qla2x00_mailbox_command(vha, mcp);
2236
2237 if (rval != QLA_SUCCESS) {
2238 /*EMPTY*/
2239 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
2240 } else {
2241 if (name != NULL) {
2242 /* This function returns name in big endian. */
2243 name[0] = MSB(mcp->mb[2]);
2244 name[1] = LSB(mcp->mb[2]);
2245 name[2] = MSB(mcp->mb[3]);
2246 name[3] = LSB(mcp->mb[3]);
2247 name[4] = MSB(mcp->mb[6]);
2248 name[5] = LSB(mcp->mb[6]);
2249 name[6] = MSB(mcp->mb[7]);
2250 name[7] = LSB(mcp->mb[7]);
2251 }
2252
2253 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
2254 "Done %s.\n", __func__);
2255 }
2256
2257 return rval;
2258 }
2259
2260 /*
2261 * qla24xx_link_initialization
2262 * Issue link initialization mailbox command.
2263 *
2264 * Input:
2265 * ha = adapter block pointer.
2266 * TARGET_QUEUE_LOCK must be released.
2267 * ADAPTER_STATE_LOCK must be released.
2268 *
2269 * Returns:
2270 * qla2x00 local function return status code.
2271 *
2272 * Context:
2273 * Kernel context.
2274 */
2275 int
qla24xx_link_initialize(scsi_qla_host_t * vha)2276 qla24xx_link_initialize(scsi_qla_host_t *vha)
2277 {
2278 int rval;
2279 mbx_cmd_t mc;
2280 mbx_cmd_t *mcp = &mc;
2281
2282 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2283 "Entered %s.\n", __func__);
2284
2285 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2286 return QLA_FUNCTION_FAILED;
2287
2288 mcp->mb[0] = MBC_LINK_INITIALIZATION;
2289 mcp->mb[1] = BIT_4;
2290 if (vha->hw->operating_mode == LOOP)
2291 mcp->mb[1] |= BIT_6;
2292 else
2293 mcp->mb[1] |= BIT_5;
2294 mcp->mb[2] = 0;
2295 mcp->mb[3] = 0;
2296 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2297 mcp->in_mb = MBX_0;
2298 mcp->tov = MBX_TOV_SECONDS;
2299 mcp->flags = 0;
2300 rval = qla2x00_mailbox_command(vha, mcp);
2301
2302 if (rval != QLA_SUCCESS) {
2303 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2304 } else {
2305 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2306 "Done %s.\n", __func__);
2307 }
2308
2309 return rval;
2310 }
2311
2312 /*
2313 * qla2x00_lip_reset
2314 * Issue LIP reset mailbox command.
2315 *
2316 * Input:
2317 * ha = adapter block pointer.
2318 * TARGET_QUEUE_LOCK must be released.
2319 * ADAPTER_STATE_LOCK must be released.
2320 *
2321 * Returns:
2322 * qla2x00 local function return status code.
2323 *
2324 * Context:
2325 * Kernel context.
2326 */
2327 int
qla2x00_lip_reset(scsi_qla_host_t * vha)2328 qla2x00_lip_reset(scsi_qla_host_t *vha)
2329 {
2330 int rval;
2331 mbx_cmd_t mc;
2332 mbx_cmd_t *mcp = &mc;
2333
2334 ql_dbg(ql_dbg_disc, vha, 0x105a,
2335 "Entered %s.\n", __func__);
2336
2337 if (IS_CNA_CAPABLE(vha->hw)) {
2338 /* Logout across all FCFs. */
2339 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2340 mcp->mb[1] = BIT_1;
2341 mcp->mb[2] = 0;
2342 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2343 } else if (IS_FWI2_CAPABLE(vha->hw)) {
2344 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2345 mcp->mb[1] = BIT_4;
2346 mcp->mb[2] = 0;
2347 mcp->mb[3] = vha->hw->loop_reset_delay;
2348 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2349 } else {
2350 mcp->mb[0] = MBC_LIP_RESET;
2351 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2352 if (HAS_EXTENDED_IDS(vha->hw)) {
2353 mcp->mb[1] = 0x00ff;
2354 mcp->mb[10] = 0;
2355 mcp->out_mb |= MBX_10;
2356 } else {
2357 mcp->mb[1] = 0xff00;
2358 }
2359 mcp->mb[2] = vha->hw->loop_reset_delay;
2360 mcp->mb[3] = 0;
2361 }
2362 mcp->in_mb = MBX_0;
2363 mcp->tov = MBX_TOV_SECONDS;
2364 mcp->flags = 0;
2365 rval = qla2x00_mailbox_command(vha, mcp);
2366
2367 if (rval != QLA_SUCCESS) {
2368 /*EMPTY*/
2369 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
2370 } else {
2371 /*EMPTY*/
2372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2373 "Done %s.\n", __func__);
2374 }
2375
2376 return rval;
2377 }
2378
2379 /*
2380 * qla2x00_send_sns
2381 * Send SNS command.
2382 *
2383 * Input:
2384 * ha = adapter block pointer.
2385 * sns = pointer for command.
2386 * cmd_size = command size.
2387 * buf_size = response/command size.
2388 * TARGET_QUEUE_LOCK must be released.
2389 * ADAPTER_STATE_LOCK must be released.
2390 *
2391 * Returns:
2392 * qla2x00 local function return status code.
2393 *
2394 * Context:
2395 * Kernel context.
2396 */
2397 int
qla2x00_send_sns(scsi_qla_host_t * vha,dma_addr_t sns_phys_address,uint16_t cmd_size,size_t buf_size)2398 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
2399 uint16_t cmd_size, size_t buf_size)
2400 {
2401 int rval;
2402 mbx_cmd_t mc;
2403 mbx_cmd_t *mcp = &mc;
2404
2405 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2406 "Entered %s.\n", __func__);
2407
2408 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
2409 "Retry cnt=%d ratov=%d total tov=%d.\n",
2410 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
2411
2412 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2413 mcp->mb[1] = cmd_size;
2414 mcp->mb[2] = MSW(sns_phys_address);
2415 mcp->mb[3] = LSW(sns_phys_address);
2416 mcp->mb[6] = MSW(MSD(sns_phys_address));
2417 mcp->mb[7] = LSW(MSD(sns_phys_address));
2418 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2419 mcp->in_mb = MBX_0|MBX_1;
2420 mcp->buf_size = buf_size;
2421 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
2422 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2423 rval = qla2x00_mailbox_command(vha, mcp);
2424
2425 if (rval != QLA_SUCCESS) {
2426 /*EMPTY*/
2427 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2428 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2429 rval, mcp->mb[0], mcp->mb[1]);
2430 } else {
2431 /*EMPTY*/
2432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2433 "Done %s.\n", __func__);
2434 }
2435
2436 return rval;
2437 }
2438
2439 int
qla24xx_login_fabric(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa,uint16_t * mb,uint8_t opt)2440 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2441 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2442 {
2443 int rval;
2444
2445 struct logio_entry_24xx *lg;
2446 dma_addr_t lg_dma;
2447 uint32_t iop[2];
2448 struct qla_hw_data *ha = vha->hw;
2449 struct req_que *req;
2450
2451 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2452 "Entered %s.\n", __func__);
2453
2454 if (vha->vp_idx && vha->qpair)
2455 req = vha->qpair->req;
2456 else
2457 req = ha->req_q_map[0];
2458
2459 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2460 if (lg == NULL) {
2461 ql_log(ql_log_warn, vha, 0x1062,
2462 "Failed to allocate login IOCB.\n");
2463 return QLA_MEMORY_ALLOC_FAILED;
2464 }
2465
2466 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2467 lg->entry_count = 1;
2468 lg->handle = make_handle(req->id, lg->handle);
2469 lg->nport_handle = cpu_to_le16(loop_id);
2470 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
2471 if (opt & BIT_0)
2472 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
2473 if (opt & BIT_1)
2474 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
2475 lg->port_id[0] = al_pa;
2476 lg->port_id[1] = area;
2477 lg->port_id[2] = domain;
2478 lg->vp_index = vha->vp_idx;
2479 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2480 (ha->r_a_tov / 10 * 2) + 2);
2481 if (rval != QLA_SUCCESS) {
2482 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2483 "Failed to issue login IOCB (%x).\n", rval);
2484 } else if (lg->entry_status != 0) {
2485 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2486 "Failed to complete IOCB -- error status (%x).\n",
2487 lg->entry_status);
2488 rval = QLA_FUNCTION_FAILED;
2489 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
2490 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2491 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2492
2493 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2494 "Failed to complete IOCB -- completion status (%x) "
2495 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2496 iop[0], iop[1]);
2497
2498 switch (iop[0]) {
2499 case LSC_SCODE_PORTID_USED:
2500 mb[0] = MBS_PORT_ID_USED;
2501 mb[1] = LSW(iop[1]);
2502 break;
2503 case LSC_SCODE_NPORT_USED:
2504 mb[0] = MBS_LOOP_ID_USED;
2505 break;
2506 case LSC_SCODE_NOLINK:
2507 case LSC_SCODE_NOIOCB:
2508 case LSC_SCODE_NOXCB:
2509 case LSC_SCODE_CMD_FAILED:
2510 case LSC_SCODE_NOFABRIC:
2511 case LSC_SCODE_FW_NOT_READY:
2512 case LSC_SCODE_NOT_LOGGED_IN:
2513 case LSC_SCODE_NOPCB:
2514 case LSC_SCODE_ELS_REJECT:
2515 case LSC_SCODE_CMD_PARAM_ERR:
2516 case LSC_SCODE_NONPORT:
2517 case LSC_SCODE_LOGGED_IN:
2518 case LSC_SCODE_NOFLOGI_ACC:
2519 default:
2520 mb[0] = MBS_COMMAND_ERROR;
2521 break;
2522 }
2523 } else {
2524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2525 "Done %s.\n", __func__);
2526
2527 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2528
2529 mb[0] = MBS_COMMAND_COMPLETE;
2530 mb[1] = 0;
2531 if (iop[0] & BIT_4) {
2532 if (iop[0] & BIT_8)
2533 mb[1] |= BIT_1;
2534 } else
2535 mb[1] = BIT_0;
2536
2537 /* Passback COS information. */
2538 mb[10] = 0;
2539 if (lg->io_parameter[7] || lg->io_parameter[8])
2540 mb[10] |= BIT_0; /* Class 2. */
2541 if (lg->io_parameter[9] || lg->io_parameter[10])
2542 mb[10] |= BIT_1; /* Class 3. */
2543 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2544 mb[10] |= BIT_7; /* Confirmed Completion
2545 * Allowed
2546 */
2547 }
2548
2549 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2550
2551 return rval;
2552 }
2553
2554 /*
2555 * qla2x00_login_fabric
2556 * Issue login fabric port mailbox command.
2557 *
2558 * Input:
2559 * ha = adapter block pointer.
2560 * loop_id = device loop ID.
2561 * domain = device domain.
2562 * area = device area.
2563 * al_pa = device AL_PA.
2564 * status = pointer for return status.
2565 * opt = command options.
2566 * TARGET_QUEUE_LOCK must be released.
2567 * ADAPTER_STATE_LOCK must be released.
2568 *
2569 * Returns:
2570 * qla2x00 local function return status code.
2571 *
2572 * Context:
2573 * Kernel context.
2574 */
2575 int
qla2x00_login_fabric(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa,uint16_t * mb,uint8_t opt)2576 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2577 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2578 {
2579 int rval;
2580 mbx_cmd_t mc;
2581 mbx_cmd_t *mcp = &mc;
2582 struct qla_hw_data *ha = vha->hw;
2583
2584 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2585 "Entered %s.\n", __func__);
2586
2587 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2588 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2589 if (HAS_EXTENDED_IDS(ha)) {
2590 mcp->mb[1] = loop_id;
2591 mcp->mb[10] = opt;
2592 mcp->out_mb |= MBX_10;
2593 } else {
2594 mcp->mb[1] = (loop_id << 8) | opt;
2595 }
2596 mcp->mb[2] = domain;
2597 mcp->mb[3] = area << 8 | al_pa;
2598
2599 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2600 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2601 mcp->flags = 0;
2602 rval = qla2x00_mailbox_command(vha, mcp);
2603
2604 /* Return mailbox statuses. */
2605 if (mb != NULL) {
2606 mb[0] = mcp->mb[0];
2607 mb[1] = mcp->mb[1];
2608 mb[2] = mcp->mb[2];
2609 mb[6] = mcp->mb[6];
2610 mb[7] = mcp->mb[7];
2611 /* COS retrieved from Get-Port-Database mailbox command. */
2612 mb[10] = 0;
2613 }
2614
2615 if (rval != QLA_SUCCESS) {
2616 /* RLU tmp code: need to change main mailbox_command function to
2617 * return ok even when the mailbox completion value is not
2618 * SUCCESS. The caller needs to be responsible to interpret
2619 * the return values of this mailbox command if we're not
2620 * to change too much of the existing code.
2621 */
2622 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2623 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2624 mcp->mb[0] == 0x4006)
2625 rval = QLA_SUCCESS;
2626
2627 /*EMPTY*/
2628 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2629 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2630 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
2631 } else {
2632 /*EMPTY*/
2633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2634 "Done %s.\n", __func__);
2635 }
2636
2637 return rval;
2638 }
2639
2640 /*
2641 * qla2x00_login_local_device
2642 * Issue login loop port mailbox command.
2643 *
2644 * Input:
2645 * ha = adapter block pointer.
2646 * loop_id = device loop ID.
2647 * opt = command options.
2648 *
2649 * Returns:
2650 * Return status code.
2651 *
2652 * Context:
2653 * Kernel context.
2654 *
2655 */
2656 int
qla2x00_login_local_device(scsi_qla_host_t * vha,fc_port_t * fcport,uint16_t * mb_ret,uint8_t opt)2657 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
2658 uint16_t *mb_ret, uint8_t opt)
2659 {
2660 int rval;
2661 mbx_cmd_t mc;
2662 mbx_cmd_t *mcp = &mc;
2663 struct qla_hw_data *ha = vha->hw;
2664
2665 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2666 "Entered %s.\n", __func__);
2667
2668 if (IS_FWI2_CAPABLE(ha))
2669 return qla24xx_login_fabric(vha, fcport->loop_id,
2670 fcport->d_id.b.domain, fcport->d_id.b.area,
2671 fcport->d_id.b.al_pa, mb_ret, opt);
2672
2673 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2674 if (HAS_EXTENDED_IDS(ha))
2675 mcp->mb[1] = fcport->loop_id;
2676 else
2677 mcp->mb[1] = fcport->loop_id << 8;
2678 mcp->mb[2] = opt;
2679 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2680 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2681 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2682 mcp->flags = 0;
2683 rval = qla2x00_mailbox_command(vha, mcp);
2684
2685 /* Return mailbox statuses. */
2686 if (mb_ret != NULL) {
2687 mb_ret[0] = mcp->mb[0];
2688 mb_ret[1] = mcp->mb[1];
2689 mb_ret[6] = mcp->mb[6];
2690 mb_ret[7] = mcp->mb[7];
2691 }
2692
2693 if (rval != QLA_SUCCESS) {
2694 /* AV tmp code: need to change main mailbox_command function to
2695 * return ok even when the mailbox completion value is not
2696 * SUCCESS. The caller needs to be responsible to interpret
2697 * the return values of this mailbox command if we're not
2698 * to change too much of the existing code.
2699 */
2700 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2701 rval = QLA_SUCCESS;
2702
2703 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2704 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2705 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
2706 } else {
2707 /*EMPTY*/
2708 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2709 "Done %s.\n", __func__);
2710 }
2711
2712 return (rval);
2713 }
2714
2715 int
qla24xx_fabric_logout(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa)2716 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2717 uint8_t area, uint8_t al_pa)
2718 {
2719 int rval;
2720 struct logio_entry_24xx *lg;
2721 dma_addr_t lg_dma;
2722 struct qla_hw_data *ha = vha->hw;
2723 struct req_que *req;
2724
2725 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2726 "Entered %s.\n", __func__);
2727
2728 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2729 if (lg == NULL) {
2730 ql_log(ql_log_warn, vha, 0x106e,
2731 "Failed to allocate logout IOCB.\n");
2732 return QLA_MEMORY_ALLOC_FAILED;
2733 }
2734
2735 req = vha->req;
2736 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2737 lg->entry_count = 1;
2738 lg->handle = make_handle(req->id, lg->handle);
2739 lg->nport_handle = cpu_to_le16(loop_id);
2740 lg->control_flags =
2741 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2742 LCF_FREE_NPORT);
2743 lg->port_id[0] = al_pa;
2744 lg->port_id[1] = area;
2745 lg->port_id[2] = domain;
2746 lg->vp_index = vha->vp_idx;
2747 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2748 (ha->r_a_tov / 10 * 2) + 2);
2749 if (rval != QLA_SUCCESS) {
2750 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2751 "Failed to issue logout IOCB (%x).\n", rval);
2752 } else if (lg->entry_status != 0) {
2753 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2754 "Failed to complete IOCB -- error status (%x).\n",
2755 lg->entry_status);
2756 rval = QLA_FUNCTION_FAILED;
2757 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
2758 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2759 "Failed to complete IOCB -- completion status (%x) "
2760 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2761 le32_to_cpu(lg->io_parameter[0]),
2762 le32_to_cpu(lg->io_parameter[1]));
2763 } else {
2764 /*EMPTY*/
2765 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2766 "Done %s.\n", __func__);
2767 }
2768
2769 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2770
2771 return rval;
2772 }
2773
2774 /*
2775 * qla2x00_fabric_logout
2776 * Issue logout fabric port mailbox command.
2777 *
2778 * Input:
2779 * ha = adapter block pointer.
2780 * loop_id = device loop ID.
2781 * TARGET_QUEUE_LOCK must be released.
2782 * ADAPTER_STATE_LOCK must be released.
2783 *
2784 * Returns:
2785 * qla2x00 local function return status code.
2786 *
2787 * Context:
2788 * Kernel context.
2789 */
2790 int
qla2x00_fabric_logout(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa)2791 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2792 uint8_t area, uint8_t al_pa)
2793 {
2794 int rval;
2795 mbx_cmd_t mc;
2796 mbx_cmd_t *mcp = &mc;
2797
2798 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2799 "Entered %s.\n", __func__);
2800
2801 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2802 mcp->out_mb = MBX_1|MBX_0;
2803 if (HAS_EXTENDED_IDS(vha->hw)) {
2804 mcp->mb[1] = loop_id;
2805 mcp->mb[10] = 0;
2806 mcp->out_mb |= MBX_10;
2807 } else {
2808 mcp->mb[1] = loop_id << 8;
2809 }
2810
2811 mcp->in_mb = MBX_1|MBX_0;
2812 mcp->tov = MBX_TOV_SECONDS;
2813 mcp->flags = 0;
2814 rval = qla2x00_mailbox_command(vha, mcp);
2815
2816 if (rval != QLA_SUCCESS) {
2817 /*EMPTY*/
2818 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2819 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
2820 } else {
2821 /*EMPTY*/
2822 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2823 "Done %s.\n", __func__);
2824 }
2825
2826 return rval;
2827 }
2828
2829 /*
2830 * qla2x00_full_login_lip
2831 * Issue full login LIP mailbox command.
2832 *
2833 * Input:
2834 * ha = adapter block pointer.
2835 * TARGET_QUEUE_LOCK must be released.
2836 * ADAPTER_STATE_LOCK must be released.
2837 *
2838 * Returns:
2839 * qla2x00 local function return status code.
2840 *
2841 * Context:
2842 * Kernel context.
2843 */
2844 int
qla2x00_full_login_lip(scsi_qla_host_t * vha)2845 qla2x00_full_login_lip(scsi_qla_host_t *vha)
2846 {
2847 int rval;
2848 mbx_cmd_t mc;
2849 mbx_cmd_t *mcp = &mc;
2850
2851 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2852 "Entered %s.\n", __func__);
2853
2854 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2855 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0;
2856 mcp->mb[2] = 0;
2857 mcp->mb[3] = 0;
2858 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2859 mcp->in_mb = MBX_0;
2860 mcp->tov = MBX_TOV_SECONDS;
2861 mcp->flags = 0;
2862 rval = qla2x00_mailbox_command(vha, mcp);
2863
2864 if (rval != QLA_SUCCESS) {
2865 /*EMPTY*/
2866 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
2867 } else {
2868 /*EMPTY*/
2869 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2870 "Done %s.\n", __func__);
2871 }
2872
2873 return rval;
2874 }
2875
2876 /*
2877 * qla2x00_get_id_list
2878 *
2879 * Input:
2880 * ha = adapter block pointer.
2881 *
2882 * Returns:
2883 * qla2x00 local function return status code.
2884 *
2885 * Context:
2886 * Kernel context.
2887 */
2888 int
qla2x00_get_id_list(scsi_qla_host_t * vha,void * id_list,dma_addr_t id_list_dma,uint16_t * entries)2889 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
2890 uint16_t *entries)
2891 {
2892 int rval;
2893 mbx_cmd_t mc;
2894 mbx_cmd_t *mcp = &mc;
2895
2896 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2897 "Entered %s.\n", __func__);
2898
2899 if (id_list == NULL)
2900 return QLA_FUNCTION_FAILED;
2901
2902 mcp->mb[0] = MBC_GET_ID_LIST;
2903 mcp->out_mb = MBX_0;
2904 if (IS_FWI2_CAPABLE(vha->hw)) {
2905 mcp->mb[2] = MSW(id_list_dma);
2906 mcp->mb[3] = LSW(id_list_dma);
2907 mcp->mb[6] = MSW(MSD(id_list_dma));
2908 mcp->mb[7] = LSW(MSD(id_list_dma));
2909 mcp->mb[8] = 0;
2910 mcp->mb[9] = vha->vp_idx;
2911 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
2912 } else {
2913 mcp->mb[1] = MSW(id_list_dma);
2914 mcp->mb[2] = LSW(id_list_dma);
2915 mcp->mb[3] = MSW(MSD(id_list_dma));
2916 mcp->mb[6] = LSW(MSD(id_list_dma));
2917 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2918 }
2919 mcp->in_mb = MBX_1|MBX_0;
2920 mcp->tov = MBX_TOV_SECONDS;
2921 mcp->flags = 0;
2922 rval = qla2x00_mailbox_command(vha, mcp);
2923
2924 if (rval != QLA_SUCCESS) {
2925 /*EMPTY*/
2926 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
2927 } else {
2928 *entries = mcp->mb[1];
2929 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2930 "Done %s.\n", __func__);
2931 }
2932
2933 return rval;
2934 }
2935
2936 /*
2937 * qla2x00_get_resource_cnts
2938 * Get current firmware resource counts.
2939 *
2940 * Input:
2941 * ha = adapter block pointer.
2942 *
2943 * Returns:
2944 * qla2x00 local function return status code.
2945 *
2946 * Context:
2947 * Kernel context.
2948 */
2949 int
qla2x00_get_resource_cnts(scsi_qla_host_t * vha)2950 qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
2951 {
2952 struct qla_hw_data *ha = vha->hw;
2953 int rval;
2954 mbx_cmd_t mc;
2955 mbx_cmd_t *mcp = &mc;
2956
2957 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2958 "Entered %s.\n", __func__);
2959
2960 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2961 mcp->out_mb = MBX_0;
2962 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2963 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
2964 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2965 mcp->in_mb |= MBX_12;
2966 mcp->tov = MBX_TOV_SECONDS;
2967 mcp->flags = 0;
2968 rval = qla2x00_mailbox_command(vha, mcp);
2969
2970 if (rval != QLA_SUCCESS) {
2971 /*EMPTY*/
2972 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2973 "Failed mb[0]=%x.\n", mcp->mb[0]);
2974 } else {
2975 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
2976 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2977 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2978 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2979 mcp->mb[11], mcp->mb[12]);
2980
2981 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2982 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2983 ha->cur_fw_xcb_count = mcp->mb[3];
2984 ha->orig_fw_xcb_count = mcp->mb[6];
2985 ha->cur_fw_iocb_count = mcp->mb[7];
2986 ha->orig_fw_iocb_count = mcp->mb[10];
2987 if (ha->flags.npiv_supported)
2988 ha->max_npiv_vports = mcp->mb[11];
2989 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
2990 IS_QLA28XX(ha))
2991 ha->fw_max_fcf_count = mcp->mb[12];
2992 }
2993
2994 return (rval);
2995 }
2996
2997 /*
2998 * qla2x00_get_fcal_position_map
2999 * Get FCAL (LILP) position map using mailbox command
3000 *
3001 * Input:
3002 * ha = adapter state pointer.
3003 * pos_map = buffer pointer (can be NULL).
3004 *
3005 * Returns:
3006 * qla2x00 local function return status code.
3007 *
3008 * Context:
3009 * Kernel context.
3010 */
3011 int
qla2x00_get_fcal_position_map(scsi_qla_host_t * vha,char * pos_map)3012 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
3013 {
3014 int rval;
3015 mbx_cmd_t mc;
3016 mbx_cmd_t *mcp = &mc;
3017 char *pmap;
3018 dma_addr_t pmap_dma;
3019 struct qla_hw_data *ha = vha->hw;
3020
3021 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
3022 "Entered %s.\n", __func__);
3023
3024 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
3025 if (pmap == NULL) {
3026 ql_log(ql_log_warn, vha, 0x1080,
3027 "Memory alloc failed.\n");
3028 return QLA_MEMORY_ALLOC_FAILED;
3029 }
3030
3031 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
3032 mcp->mb[2] = MSW(pmap_dma);
3033 mcp->mb[3] = LSW(pmap_dma);
3034 mcp->mb[6] = MSW(MSD(pmap_dma));
3035 mcp->mb[7] = LSW(MSD(pmap_dma));
3036 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3037 mcp->in_mb = MBX_1|MBX_0;
3038 mcp->buf_size = FCAL_MAP_SIZE;
3039 mcp->flags = MBX_DMA_IN;
3040 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
3041 rval = qla2x00_mailbox_command(vha, mcp);
3042
3043 if (rval == QLA_SUCCESS) {
3044 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
3045 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
3046 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
3047 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
3048 pmap, pmap[0] + 1);
3049
3050 if (pos_map)
3051 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
3052 }
3053 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
3054
3055 if (rval != QLA_SUCCESS) {
3056 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
3057 } else {
3058 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
3059 "Done %s.\n", __func__);
3060 }
3061
3062 return rval;
3063 }
3064
3065 /*
3066 * qla2x00_get_link_status
3067 *
3068 * Input:
3069 * ha = adapter block pointer.
3070 * loop_id = device loop ID.
3071 * ret_buf = pointer to link status return buffer.
3072 *
3073 * Returns:
3074 * 0 = success.
3075 * BIT_0 = mem alloc error.
3076 * BIT_1 = mailbox error.
3077 */
3078 int
qla2x00_get_link_status(scsi_qla_host_t * vha,uint16_t loop_id,struct link_statistics * stats,dma_addr_t stats_dma)3079 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
3080 struct link_statistics *stats, dma_addr_t stats_dma)
3081 {
3082 int rval;
3083 mbx_cmd_t mc;
3084 mbx_cmd_t *mcp = &mc;
3085 uint32_t *iter = (uint32_t *)stats;
3086 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
3087 struct qla_hw_data *ha = vha->hw;
3088
3089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
3090 "Entered %s.\n", __func__);
3091
3092 mcp->mb[0] = MBC_GET_LINK_STATUS;
3093 mcp->mb[2] = MSW(LSD(stats_dma));
3094 mcp->mb[3] = LSW(LSD(stats_dma));
3095 mcp->mb[6] = MSW(MSD(stats_dma));
3096 mcp->mb[7] = LSW(MSD(stats_dma));
3097 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3098 mcp->in_mb = MBX_0;
3099 if (IS_FWI2_CAPABLE(ha)) {
3100 mcp->mb[1] = loop_id;
3101 mcp->mb[4] = 0;
3102 mcp->mb[10] = 0;
3103 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
3104 mcp->in_mb |= MBX_1;
3105 } else if (HAS_EXTENDED_IDS(ha)) {
3106 mcp->mb[1] = loop_id;
3107 mcp->mb[10] = 0;
3108 mcp->out_mb |= MBX_10|MBX_1;
3109 } else {
3110 mcp->mb[1] = loop_id << 8;
3111 mcp->out_mb |= MBX_1;
3112 }
3113 mcp->tov = MBX_TOV_SECONDS;
3114 mcp->flags = IOCTL_CMD;
3115 rval = qla2x00_mailbox_command(vha, mcp);
3116
3117 if (rval == QLA_SUCCESS) {
3118 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3119 ql_dbg(ql_dbg_mbx, vha, 0x1085,
3120 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3121 rval = QLA_FUNCTION_FAILED;
3122 } else {
3123 /* Re-endianize - firmware data is le32. */
3124 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
3125 "Done %s.\n", __func__);
3126 for ( ; dwords--; iter++)
3127 le32_to_cpus(iter);
3128 }
3129 } else {
3130 /* Failed. */
3131 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
3132 }
3133
3134 return rval;
3135 }
3136
3137 int
qla24xx_get_isp_stats(scsi_qla_host_t * vha,struct link_statistics * stats,dma_addr_t stats_dma,uint16_t options)3138 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
3139 dma_addr_t stats_dma, uint16_t options)
3140 {
3141 int rval;
3142 mbx_cmd_t mc;
3143 mbx_cmd_t *mcp = &mc;
3144 uint32_t *iter = (uint32_t *)stats;
3145 ushort dwords = sizeof(*stats)/sizeof(*iter);
3146
3147 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
3148 "Entered %s.\n", __func__);
3149
3150 memset(&mc, 0, sizeof(mc));
3151 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
3152 mc.mb[2] = MSW(LSD(stats_dma));
3153 mc.mb[3] = LSW(LSD(stats_dma));
3154 mc.mb[6] = MSW(MSD(stats_dma));
3155 mc.mb[7] = LSW(MSD(stats_dma));
3156 mc.mb[8] = dwords;
3157 mc.mb[9] = vha->vp_idx;
3158 mc.mb[10] = options;
3159
3160 rval = qla24xx_send_mb_cmd(vha, &mc);
3161
3162 if (rval == QLA_SUCCESS) {
3163 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3164 ql_dbg(ql_dbg_mbx, vha, 0x1089,
3165 "Failed mb[0]=%x.\n", mcp->mb[0]);
3166 rval = QLA_FUNCTION_FAILED;
3167 } else {
3168 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
3169 "Done %s.\n", __func__);
3170 /* Re-endianize - firmware data is le32. */
3171 for ( ; dwords--; iter++)
3172 le32_to_cpus(iter);
3173 }
3174 } else {
3175 /* Failed. */
3176 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
3177 }
3178
3179 return rval;
3180 }
3181
3182 int
qla24xx_abort_command(srb_t * sp)3183 qla24xx_abort_command(srb_t *sp)
3184 {
3185 int rval;
3186 unsigned long flags = 0;
3187
3188 struct abort_entry_24xx *abt;
3189 dma_addr_t abt_dma;
3190 uint32_t handle;
3191 fc_port_t *fcport = sp->fcport;
3192 struct scsi_qla_host *vha = fcport->vha;
3193 struct qla_hw_data *ha = vha->hw;
3194 struct req_que *req = vha->req;
3195 struct qla_qpair *qpair = sp->qpair;
3196
3197 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3198 "Entered %s.\n", __func__);
3199
3200 if (sp->qpair)
3201 req = sp->qpair->req;
3202 else
3203 return QLA_FUNCTION_FAILED;
3204
3205 if (ql2xasynctmfenable)
3206 return qla24xx_async_abort_command(sp);
3207
3208 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
3209 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
3210 if (req->outstanding_cmds[handle] == sp)
3211 break;
3212 }
3213 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
3214 if (handle == req->num_outstanding_cmds) {
3215 /* Command not found. */
3216 return QLA_FUNCTION_FAILED;
3217 }
3218
3219 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
3220 if (abt == NULL) {
3221 ql_log(ql_log_warn, vha, 0x108d,
3222 "Failed to allocate abort IOCB.\n");
3223 return QLA_MEMORY_ALLOC_FAILED;
3224 }
3225
3226 abt->entry_type = ABORT_IOCB_TYPE;
3227 abt->entry_count = 1;
3228 abt->handle = make_handle(req->id, abt->handle);
3229 abt->nport_handle = cpu_to_le16(fcport->loop_id);
3230 abt->handle_to_abort = make_handle(req->id, handle);
3231 abt->port_id[0] = fcport->d_id.b.al_pa;
3232 abt->port_id[1] = fcport->d_id.b.area;
3233 abt->port_id[2] = fcport->d_id.b.domain;
3234 abt->vp_index = fcport->vha->vp_idx;
3235
3236 abt->req_que_no = cpu_to_le16(req->id);
3237
3238 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
3239 if (rval != QLA_SUCCESS) {
3240 ql_dbg(ql_dbg_mbx, vha, 0x108e,
3241 "Failed to issue IOCB (%x).\n", rval);
3242 } else if (abt->entry_status != 0) {
3243 ql_dbg(ql_dbg_mbx, vha, 0x108f,
3244 "Failed to complete IOCB -- error status (%x).\n",
3245 abt->entry_status);
3246 rval = QLA_FUNCTION_FAILED;
3247 } else if (abt->nport_handle != cpu_to_le16(0)) {
3248 ql_dbg(ql_dbg_mbx, vha, 0x1090,
3249 "Failed to complete IOCB -- completion status (%x).\n",
3250 le16_to_cpu(abt->nport_handle));
3251 if (abt->nport_handle == cpu_to_le16(CS_IOCB_ERROR))
3252 rval = QLA_FUNCTION_PARAMETER_ERROR;
3253 else
3254 rval = QLA_FUNCTION_FAILED;
3255 } else {
3256 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
3257 "Done %s.\n", __func__);
3258 }
3259
3260 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
3261
3262 return rval;
3263 }
3264
3265 struct tsk_mgmt_cmd {
3266 union {
3267 struct tsk_mgmt_entry tsk;
3268 struct sts_entry_24xx sts;
3269 } p;
3270 };
3271
3272 static int
__qla24xx_issue_tmf(char * name,uint32_t type,struct fc_port * fcport,uint64_t l,int tag)3273 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
3274 uint64_t l, int tag)
3275 {
3276 int rval, rval2;
3277 struct tsk_mgmt_cmd *tsk;
3278 struct sts_entry_24xx *sts;
3279 dma_addr_t tsk_dma;
3280 scsi_qla_host_t *vha;
3281 struct qla_hw_data *ha;
3282 struct req_que *req;
3283 struct qla_qpair *qpair;
3284
3285 vha = fcport->vha;
3286 ha = vha->hw;
3287 req = vha->req;
3288
3289 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3290 "Entered %s.\n", __func__);
3291
3292 if (vha->vp_idx && vha->qpair) {
3293 /* NPIV port */
3294 qpair = vha->qpair;
3295 req = qpair->req;
3296 }
3297
3298 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
3299 if (tsk == NULL) {
3300 ql_log(ql_log_warn, vha, 0x1093,
3301 "Failed to allocate task management IOCB.\n");
3302 return QLA_MEMORY_ALLOC_FAILED;
3303 }
3304
3305 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3306 tsk->p.tsk.entry_count = 1;
3307 tsk->p.tsk.handle = make_handle(req->id, tsk->p.tsk.handle);
3308 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
3309 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
3310 tsk->p.tsk.control_flags = cpu_to_le32(type);
3311 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3312 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3313 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
3314 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
3315 if (type == TCF_LUN_RESET) {
3316 int_to_scsilun(l, &tsk->p.tsk.lun);
3317 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3318 sizeof(tsk->p.tsk.lun));
3319 }
3320
3321 sts = &tsk->p.sts;
3322 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
3323 if (rval != QLA_SUCCESS) {
3324 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3325 "Failed to issue %s reset IOCB (%x).\n", name, rval);
3326 } else if (sts->entry_status != 0) {
3327 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3328 "Failed to complete IOCB -- error status (%x).\n",
3329 sts->entry_status);
3330 rval = QLA_FUNCTION_FAILED;
3331 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
3332 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3333 "Failed to complete IOCB -- completion status (%x).\n",
3334 le16_to_cpu(sts->comp_status));
3335 rval = QLA_FUNCTION_FAILED;
3336 } else if (le16_to_cpu(sts->scsi_status) &
3337 SS_RESPONSE_INFO_LEN_VALID) {
3338 if (le32_to_cpu(sts->rsp_data_len) < 4) {
3339 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
3340 "Ignoring inconsistent data length -- not enough "
3341 "response info (%d).\n",
3342 le32_to_cpu(sts->rsp_data_len));
3343 } else if (sts->data[3]) {
3344 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3345 "Failed to complete IOCB -- response (%x).\n",
3346 sts->data[3]);
3347 rval = QLA_FUNCTION_FAILED;
3348 }
3349 }
3350
3351 /* Issue marker IOCB. */
3352 rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l,
3353 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
3354 if (rval2 != QLA_SUCCESS) {
3355 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3356 "Failed to issue marker IOCB (%x).\n", rval2);
3357 } else {
3358 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3359 "Done %s.\n", __func__);
3360 }
3361
3362 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
3363
3364 return rval;
3365 }
3366
3367 int
qla24xx_abort_target(struct fc_port * fcport,uint64_t l,int tag)3368 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
3369 {
3370 struct qla_hw_data *ha = fcport->vha->hw;
3371
3372 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3373 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3374
3375 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
3376 }
3377
3378 int
qla24xx_lun_reset(struct fc_port * fcport,uint64_t l,int tag)3379 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
3380 {
3381 struct qla_hw_data *ha = fcport->vha->hw;
3382
3383 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3384 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3385
3386 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
3387 }
3388
3389 int
qla2x00_system_error(scsi_qla_host_t * vha)3390 qla2x00_system_error(scsi_qla_host_t *vha)
3391 {
3392 int rval;
3393 mbx_cmd_t mc;
3394 mbx_cmd_t *mcp = &mc;
3395 struct qla_hw_data *ha = vha->hw;
3396
3397 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
3398 return QLA_FUNCTION_FAILED;
3399
3400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3401 "Entered %s.\n", __func__);
3402
3403 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3404 mcp->out_mb = MBX_0;
3405 mcp->in_mb = MBX_0;
3406 mcp->tov = 5;
3407 mcp->flags = 0;
3408 rval = qla2x00_mailbox_command(vha, mcp);
3409
3410 if (rval != QLA_SUCCESS) {
3411 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
3412 } else {
3413 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3414 "Done %s.\n", __func__);
3415 }
3416
3417 return rval;
3418 }
3419
3420 int
qla2x00_write_serdes_word(scsi_qla_host_t * vha,uint16_t addr,uint16_t data)3421 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3422 {
3423 int rval;
3424 mbx_cmd_t mc;
3425 mbx_cmd_t *mcp = &mc;
3426
3427 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3428 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3429 return QLA_FUNCTION_FAILED;
3430
3431 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3432 "Entered %s.\n", __func__);
3433
3434 mcp->mb[0] = MBC_WRITE_SERDES;
3435 mcp->mb[1] = addr;
3436 if (IS_QLA2031(vha->hw))
3437 mcp->mb[2] = data & 0xff;
3438 else
3439 mcp->mb[2] = data;
3440
3441 mcp->mb[3] = 0;
3442 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3443 mcp->in_mb = MBX_0;
3444 mcp->tov = MBX_TOV_SECONDS;
3445 mcp->flags = 0;
3446 rval = qla2x00_mailbox_command(vha, mcp);
3447
3448 if (rval != QLA_SUCCESS) {
3449 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3450 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3451 } else {
3452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3453 "Done %s.\n", __func__);
3454 }
3455
3456 return rval;
3457 }
3458
3459 int
qla2x00_read_serdes_word(scsi_qla_host_t * vha,uint16_t addr,uint16_t * data)3460 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3461 {
3462 int rval;
3463 mbx_cmd_t mc;
3464 mbx_cmd_t *mcp = &mc;
3465
3466 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3467 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3468 return QLA_FUNCTION_FAILED;
3469
3470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3471 "Entered %s.\n", __func__);
3472
3473 mcp->mb[0] = MBC_READ_SERDES;
3474 mcp->mb[1] = addr;
3475 mcp->mb[3] = 0;
3476 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3477 mcp->in_mb = MBX_1|MBX_0;
3478 mcp->tov = MBX_TOV_SECONDS;
3479 mcp->flags = 0;
3480 rval = qla2x00_mailbox_command(vha, mcp);
3481
3482 if (IS_QLA2031(vha->hw))
3483 *data = mcp->mb[1] & 0xff;
3484 else
3485 *data = mcp->mb[1];
3486
3487 if (rval != QLA_SUCCESS) {
3488 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3489 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3490 } else {
3491 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3492 "Done %s.\n", __func__);
3493 }
3494
3495 return rval;
3496 }
3497
3498 int
qla8044_write_serdes_word(scsi_qla_host_t * vha,uint32_t addr,uint32_t data)3499 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3500 {
3501 int rval;
3502 mbx_cmd_t mc;
3503 mbx_cmd_t *mcp = &mc;
3504
3505 if (!IS_QLA8044(vha->hw))
3506 return QLA_FUNCTION_FAILED;
3507
3508 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
3509 "Entered %s.\n", __func__);
3510
3511 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3512 mcp->mb[1] = HCS_WRITE_SERDES;
3513 mcp->mb[3] = LSW(addr);
3514 mcp->mb[4] = MSW(addr);
3515 mcp->mb[5] = LSW(data);
3516 mcp->mb[6] = MSW(data);
3517 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3518 mcp->in_mb = MBX_0;
3519 mcp->tov = MBX_TOV_SECONDS;
3520 mcp->flags = 0;
3521 rval = qla2x00_mailbox_command(vha, mcp);
3522
3523 if (rval != QLA_SUCCESS) {
3524 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
3525 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3526 } else {
3527 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3528 "Done %s.\n", __func__);
3529 }
3530
3531 return rval;
3532 }
3533
3534 int
qla8044_read_serdes_word(scsi_qla_host_t * vha,uint32_t addr,uint32_t * data)3535 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3536 {
3537 int rval;
3538 mbx_cmd_t mc;
3539 mbx_cmd_t *mcp = &mc;
3540
3541 if (!IS_QLA8044(vha->hw))
3542 return QLA_FUNCTION_FAILED;
3543
3544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3545 "Entered %s.\n", __func__);
3546
3547 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3548 mcp->mb[1] = HCS_READ_SERDES;
3549 mcp->mb[3] = LSW(addr);
3550 mcp->mb[4] = MSW(addr);
3551 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3552 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3553 mcp->tov = MBX_TOV_SECONDS;
3554 mcp->flags = 0;
3555 rval = qla2x00_mailbox_command(vha, mcp);
3556
3557 *data = mcp->mb[2] << 16 | mcp->mb[1];
3558
3559 if (rval != QLA_SUCCESS) {
3560 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3561 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3562 } else {
3563 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3564 "Done %s.\n", __func__);
3565 }
3566
3567 return rval;
3568 }
3569
3570 /**
3571 * qla2x00_set_serdes_params() -
3572 * @vha: HA context
3573 * @sw_em_1g: serial link options
3574 * @sw_em_2g: serial link options
3575 * @sw_em_4g: serial link options
3576 *
3577 * Returns
3578 */
3579 int
qla2x00_set_serdes_params(scsi_qla_host_t * vha,uint16_t sw_em_1g,uint16_t sw_em_2g,uint16_t sw_em_4g)3580 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
3581 uint16_t sw_em_2g, uint16_t sw_em_4g)
3582 {
3583 int rval;
3584 mbx_cmd_t mc;
3585 mbx_cmd_t *mcp = &mc;
3586
3587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3588 "Entered %s.\n", __func__);
3589
3590 mcp->mb[0] = MBC_SERDES_PARAMS;
3591 mcp->mb[1] = BIT_0;
3592 mcp->mb[2] = sw_em_1g | BIT_15;
3593 mcp->mb[3] = sw_em_2g | BIT_15;
3594 mcp->mb[4] = sw_em_4g | BIT_15;
3595 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3596 mcp->in_mb = MBX_0;
3597 mcp->tov = MBX_TOV_SECONDS;
3598 mcp->flags = 0;
3599 rval = qla2x00_mailbox_command(vha, mcp);
3600
3601 if (rval != QLA_SUCCESS) {
3602 /*EMPTY*/
3603 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3604 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3605 } else {
3606 /*EMPTY*/
3607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3608 "Done %s.\n", __func__);
3609 }
3610
3611 return rval;
3612 }
3613
3614 int
qla2x00_stop_firmware(scsi_qla_host_t * vha)3615 qla2x00_stop_firmware(scsi_qla_host_t *vha)
3616 {
3617 int rval;
3618 mbx_cmd_t mc;
3619 mbx_cmd_t *mcp = &mc;
3620
3621 if (!IS_FWI2_CAPABLE(vha->hw))
3622 return QLA_FUNCTION_FAILED;
3623
3624 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3625 "Entered %s.\n", __func__);
3626
3627 mcp->mb[0] = MBC_STOP_FIRMWARE;
3628 mcp->mb[1] = 0;
3629 mcp->out_mb = MBX_1|MBX_0;
3630 mcp->in_mb = MBX_0;
3631 mcp->tov = 5;
3632 mcp->flags = 0;
3633 rval = qla2x00_mailbox_command(vha, mcp);
3634
3635 if (rval != QLA_SUCCESS) {
3636 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
3637 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3638 rval = QLA_INVALID_COMMAND;
3639 } else {
3640 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3641 "Done %s.\n", __func__);
3642 }
3643
3644 return rval;
3645 }
3646
3647 int
qla2x00_enable_eft_trace(scsi_qla_host_t * vha,dma_addr_t eft_dma,uint16_t buffers)3648 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
3649 uint16_t buffers)
3650 {
3651 int rval;
3652 mbx_cmd_t mc;
3653 mbx_cmd_t *mcp = &mc;
3654
3655 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3656 "Entered %s.\n", __func__);
3657
3658 if (!IS_FWI2_CAPABLE(vha->hw))
3659 return QLA_FUNCTION_FAILED;
3660
3661 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3662 return QLA_FUNCTION_FAILED;
3663
3664 mcp->mb[0] = MBC_TRACE_CONTROL;
3665 mcp->mb[1] = TC_EFT_ENABLE;
3666 mcp->mb[2] = LSW(eft_dma);
3667 mcp->mb[3] = MSW(eft_dma);
3668 mcp->mb[4] = LSW(MSD(eft_dma));
3669 mcp->mb[5] = MSW(MSD(eft_dma));
3670 mcp->mb[6] = buffers;
3671 mcp->mb[7] = TC_AEN_DISABLE;
3672 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3673 mcp->in_mb = MBX_1|MBX_0;
3674 mcp->tov = MBX_TOV_SECONDS;
3675 mcp->flags = 0;
3676 rval = qla2x00_mailbox_command(vha, mcp);
3677 if (rval != QLA_SUCCESS) {
3678 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3679 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3680 rval, mcp->mb[0], mcp->mb[1]);
3681 } else {
3682 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3683 "Done %s.\n", __func__);
3684 }
3685
3686 return rval;
3687 }
3688
3689 int
qla2x00_disable_eft_trace(scsi_qla_host_t * vha)3690 qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
3691 {
3692 int rval;
3693 mbx_cmd_t mc;
3694 mbx_cmd_t *mcp = &mc;
3695
3696 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3697 "Entered %s.\n", __func__);
3698
3699 if (!IS_FWI2_CAPABLE(vha->hw))
3700 return QLA_FUNCTION_FAILED;
3701
3702 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3703 return QLA_FUNCTION_FAILED;
3704
3705 mcp->mb[0] = MBC_TRACE_CONTROL;
3706 mcp->mb[1] = TC_EFT_DISABLE;
3707 mcp->out_mb = MBX_1|MBX_0;
3708 mcp->in_mb = MBX_1|MBX_0;
3709 mcp->tov = MBX_TOV_SECONDS;
3710 mcp->flags = 0;
3711 rval = qla2x00_mailbox_command(vha, mcp);
3712 if (rval != QLA_SUCCESS) {
3713 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3714 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3715 rval, mcp->mb[0], mcp->mb[1]);
3716 } else {
3717 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3718 "Done %s.\n", __func__);
3719 }
3720
3721 return rval;
3722 }
3723
3724 int
qla2x00_enable_fce_trace(scsi_qla_host_t * vha,dma_addr_t fce_dma,uint16_t buffers,uint16_t * mb,uint32_t * dwords)3725 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
3726 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3727 {
3728 int rval;
3729 mbx_cmd_t mc;
3730 mbx_cmd_t *mcp = &mc;
3731
3732 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3733 "Entered %s.\n", __func__);
3734
3735 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
3736 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
3737 !IS_QLA28XX(vha->hw))
3738 return QLA_FUNCTION_FAILED;
3739
3740 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3741 return QLA_FUNCTION_FAILED;
3742
3743 mcp->mb[0] = MBC_TRACE_CONTROL;
3744 mcp->mb[1] = TC_FCE_ENABLE;
3745 mcp->mb[2] = LSW(fce_dma);
3746 mcp->mb[3] = MSW(fce_dma);
3747 mcp->mb[4] = LSW(MSD(fce_dma));
3748 mcp->mb[5] = MSW(MSD(fce_dma));
3749 mcp->mb[6] = buffers;
3750 mcp->mb[7] = TC_AEN_DISABLE;
3751 mcp->mb[8] = 0;
3752 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3753 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3754 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3755 MBX_1|MBX_0;
3756 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3757 mcp->tov = MBX_TOV_SECONDS;
3758 mcp->flags = 0;
3759 rval = qla2x00_mailbox_command(vha, mcp);
3760 if (rval != QLA_SUCCESS) {
3761 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3762 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3763 rval, mcp->mb[0], mcp->mb[1]);
3764 } else {
3765 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3766 "Done %s.\n", __func__);
3767
3768 if (mb)
3769 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3770 if (dwords)
3771 *dwords = buffers;
3772 }
3773
3774 return rval;
3775 }
3776
3777 int
qla2x00_disable_fce_trace(scsi_qla_host_t * vha,uint64_t * wr,uint64_t * rd)3778 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
3779 {
3780 int rval;
3781 mbx_cmd_t mc;
3782 mbx_cmd_t *mcp = &mc;
3783
3784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3785 "Entered %s.\n", __func__);
3786
3787 if (!IS_FWI2_CAPABLE(vha->hw))
3788 return QLA_FUNCTION_FAILED;
3789
3790 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3791 return QLA_FUNCTION_FAILED;
3792
3793 mcp->mb[0] = MBC_TRACE_CONTROL;
3794 mcp->mb[1] = TC_FCE_DISABLE;
3795 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3796 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3797 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3798 MBX_1|MBX_0;
3799 mcp->tov = MBX_TOV_SECONDS;
3800 mcp->flags = 0;
3801 rval = qla2x00_mailbox_command(vha, mcp);
3802 if (rval != QLA_SUCCESS) {
3803 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3804 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3805 rval, mcp->mb[0], mcp->mb[1]);
3806 } else {
3807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3808 "Done %s.\n", __func__);
3809
3810 if (wr)
3811 *wr = (uint64_t) mcp->mb[5] << 48 |
3812 (uint64_t) mcp->mb[4] << 32 |
3813 (uint64_t) mcp->mb[3] << 16 |
3814 (uint64_t) mcp->mb[2];
3815 if (rd)
3816 *rd = (uint64_t) mcp->mb[9] << 48 |
3817 (uint64_t) mcp->mb[8] << 32 |
3818 (uint64_t) mcp->mb[7] << 16 |
3819 (uint64_t) mcp->mb[6];
3820 }
3821
3822 return rval;
3823 }
3824
3825 int
qla2x00_get_idma_speed(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t * port_speed,uint16_t * mb)3826 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3827 uint16_t *port_speed, uint16_t *mb)
3828 {
3829 int rval;
3830 mbx_cmd_t mc;
3831 mbx_cmd_t *mcp = &mc;
3832
3833 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3834 "Entered %s.\n", __func__);
3835
3836 if (!IS_IIDMA_CAPABLE(vha->hw))
3837 return QLA_FUNCTION_FAILED;
3838
3839 mcp->mb[0] = MBC_PORT_PARAMS;
3840 mcp->mb[1] = loop_id;
3841 mcp->mb[2] = mcp->mb[3] = 0;
3842 mcp->mb[9] = vha->vp_idx;
3843 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3844 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3845 mcp->tov = MBX_TOV_SECONDS;
3846 mcp->flags = 0;
3847 rval = qla2x00_mailbox_command(vha, mcp);
3848
3849 /* Return mailbox statuses. */
3850 if (mb) {
3851 mb[0] = mcp->mb[0];
3852 mb[1] = mcp->mb[1];
3853 mb[3] = mcp->mb[3];
3854 }
3855
3856 if (rval != QLA_SUCCESS) {
3857 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
3858 } else {
3859 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3860 "Done %s.\n", __func__);
3861 if (port_speed)
3862 *port_speed = mcp->mb[3];
3863 }
3864
3865 return rval;
3866 }
3867
3868 int
qla2x00_set_idma_speed(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t port_speed,uint16_t * mb)3869 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3870 uint16_t port_speed, uint16_t *mb)
3871 {
3872 int rval;
3873 mbx_cmd_t mc;
3874 mbx_cmd_t *mcp = &mc;
3875
3876 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3877 "Entered %s.\n", __func__);
3878
3879 if (!IS_IIDMA_CAPABLE(vha->hw))
3880 return QLA_FUNCTION_FAILED;
3881
3882 mcp->mb[0] = MBC_PORT_PARAMS;
3883 mcp->mb[1] = loop_id;
3884 mcp->mb[2] = BIT_0;
3885 mcp->mb[3] = port_speed & 0x3F;
3886 mcp->mb[9] = vha->vp_idx;
3887 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3888 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3889 mcp->tov = MBX_TOV_SECONDS;
3890 mcp->flags = 0;
3891 rval = qla2x00_mailbox_command(vha, mcp);
3892
3893 /* Return mailbox statuses. */
3894 if (mb) {
3895 mb[0] = mcp->mb[0];
3896 mb[1] = mcp->mb[1];
3897 mb[3] = mcp->mb[3];
3898 }
3899
3900 if (rval != QLA_SUCCESS) {
3901 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3902 "Failed=%x.\n", rval);
3903 } else {
3904 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3905 "Done %s.\n", __func__);
3906 }
3907
3908 return rval;
3909 }
3910
3911 void
qla24xx_report_id_acquisition(scsi_qla_host_t * vha,struct vp_rpt_id_entry_24xx * rptid_entry)3912 qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
3913 struct vp_rpt_id_entry_24xx *rptid_entry)
3914 {
3915 struct qla_hw_data *ha = vha->hw;
3916 scsi_qla_host_t *vp = NULL;
3917 unsigned long flags;
3918 int found;
3919 port_id_t id;
3920 struct fc_port *fcport;
3921
3922 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3923 "Entered %s.\n", __func__);
3924
3925 if (rptid_entry->entry_status != 0)
3926 return;
3927
3928 id.b.domain = rptid_entry->port_id[2];
3929 id.b.area = rptid_entry->port_id[1];
3930 id.b.al_pa = rptid_entry->port_id[0];
3931 id.b.rsvd_1 = 0;
3932 ha->flags.n2n_ae = 0;
3933
3934 if (rptid_entry->format == 0) {
3935 /* loop */
3936 ql_dbg(ql_dbg_async, vha, 0x10b7,
3937 "Format 0 : Number of VPs setup %d, number of "
3938 "VPs acquired %d.\n", rptid_entry->vp_setup,
3939 rptid_entry->vp_acquired);
3940 ql_dbg(ql_dbg_async, vha, 0x10b8,
3941 "Primary port id %02x%02x%02x.\n",
3942 rptid_entry->port_id[2], rptid_entry->port_id[1],
3943 rptid_entry->port_id[0]);
3944 ha->current_topology = ISP_CFG_NL;
3945 qlt_update_host_map(vha, id);
3946
3947 } else if (rptid_entry->format == 1) {
3948 /* fabric */
3949 ql_dbg(ql_dbg_async, vha, 0x10b9,
3950 "Format 1: VP[%d] enabled - status %d - with "
3951 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3952 rptid_entry->vp_status,
3953 rptid_entry->port_id[2], rptid_entry->port_id[1],
3954 rptid_entry->port_id[0]);
3955 ql_dbg(ql_dbg_async, vha, 0x5075,
3956 "Format 1: Remote WWPN %8phC.\n",
3957 rptid_entry->u.f1.port_name);
3958
3959 ql_dbg(ql_dbg_async, vha, 0x5075,
3960 "Format 1: WWPN %8phC.\n",
3961 vha->port_name);
3962
3963 switch (rptid_entry->u.f1.flags & TOPO_MASK) {
3964 case TOPO_N2N:
3965 ha->current_topology = ISP_CFG_N;
3966 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
3967 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3968 fcport->scan_state = QLA_FCPORT_SCAN;
3969 fcport->n2n_flag = 0;
3970 }
3971 id.b24 = 0;
3972 if (wwn_to_u64(vha->port_name) >
3973 wwn_to_u64(rptid_entry->u.f1.port_name)) {
3974 vha->d_id.b24 = 0;
3975 vha->d_id.b.al_pa = 1;
3976 ha->flags.n2n_bigger = 1;
3977
3978 id.b.al_pa = 2;
3979 ql_dbg(ql_dbg_async, vha, 0x5075,
3980 "Format 1: assign local id %x remote id %x\n",
3981 vha->d_id.b24, id.b24);
3982 } else {
3983 ql_dbg(ql_dbg_async, vha, 0x5075,
3984 "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3985 rptid_entry->u.f1.port_name);
3986 ha->flags.n2n_bigger = 0;
3987 }
3988
3989 fcport = qla2x00_find_fcport_by_wwpn(vha,
3990 rptid_entry->u.f1.port_name, 1);
3991 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3992
3993
3994 if (fcport) {
3995 fcport->plogi_nack_done_deadline = jiffies + HZ;
3996 fcport->dm_login_expire = jiffies +
3997 QLA_N2N_WAIT_TIME * HZ;
3998 fcport->scan_state = QLA_FCPORT_FOUND;
3999 fcport->n2n_flag = 1;
4000 fcport->keep_nport_handle = 1;
4001 fcport->fc4_type = FS_FC4TYPE_FCP;
4002 if (vha->flags.nvme_enabled)
4003 fcport->fc4_type |= FS_FC4TYPE_NVME;
4004
4005 if (wwn_to_u64(vha->port_name) >
4006 wwn_to_u64(fcport->port_name)) {
4007 fcport->d_id = id;
4008 }
4009
4010 switch (fcport->disc_state) {
4011 case DSC_DELETED:
4012 set_bit(RELOGIN_NEEDED,
4013 &vha->dpc_flags);
4014 break;
4015 case DSC_DELETE_PEND:
4016 break;
4017 default:
4018 qlt_schedule_sess_for_deletion(fcport);
4019 break;
4020 }
4021 } else {
4022 qla24xx_post_newsess_work(vha, &id,
4023 rptid_entry->u.f1.port_name,
4024 rptid_entry->u.f1.node_name,
4025 NULL,
4026 FS_FCP_IS_N2N);
4027 }
4028
4029 /* if our portname is higher then initiate N2N login */
4030
4031 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
4032 return;
4033 break;
4034 case TOPO_FL:
4035 ha->current_topology = ISP_CFG_FL;
4036 break;
4037 case TOPO_F:
4038 ha->current_topology = ISP_CFG_F;
4039 break;
4040 default:
4041 break;
4042 }
4043
4044 ha->flags.gpsc_supported = 1;
4045 ha->current_topology = ISP_CFG_F;
4046 /* buffer to buffer credit flag */
4047 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
4048
4049 if (rptid_entry->vp_idx == 0) {
4050 if (rptid_entry->vp_status == VP_STAT_COMPL) {
4051 /* FA-WWN is only for physical port */
4052 if (qla_ini_mode_enabled(vha) &&
4053 ha->flags.fawwpn_enabled &&
4054 (rptid_entry->u.f1.flags &
4055 BIT_6)) {
4056 memcpy(vha->port_name,
4057 rptid_entry->u.f1.port_name,
4058 WWN_SIZE);
4059 }
4060
4061 qlt_update_host_map(vha, id);
4062 }
4063
4064 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
4065 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
4066 } else {
4067 if (rptid_entry->vp_status != VP_STAT_COMPL &&
4068 rptid_entry->vp_status != VP_STAT_ID_CHG) {
4069 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
4070 "Could not acquire ID for VP[%d].\n",
4071 rptid_entry->vp_idx);
4072 return;
4073 }
4074
4075 found = 0;
4076 spin_lock_irqsave(&ha->vport_slock, flags);
4077 list_for_each_entry(vp, &ha->vp_list, list) {
4078 if (rptid_entry->vp_idx == vp->vp_idx) {
4079 found = 1;
4080 break;
4081 }
4082 }
4083 spin_unlock_irqrestore(&ha->vport_slock, flags);
4084
4085 if (!found)
4086 return;
4087
4088 qlt_update_host_map(vp, id);
4089
4090 /*
4091 * Cannot configure here as we are still sitting on the
4092 * response queue. Handle it in dpc context.
4093 */
4094 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
4095 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
4096 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
4097 }
4098 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
4099 qla2xxx_wake_dpc(vha);
4100 } else if (rptid_entry->format == 2) {
4101 ql_dbg(ql_dbg_async, vha, 0x505f,
4102 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
4103 rptid_entry->port_id[2], rptid_entry->port_id[1],
4104 rptid_entry->port_id[0]);
4105
4106 ql_dbg(ql_dbg_async, vha, 0x5075,
4107 "N2N: Remote WWPN %8phC.\n",
4108 rptid_entry->u.f2.port_name);
4109
4110 /* N2N. direct connect */
4111 ha->current_topology = ISP_CFG_N;
4112 ha->flags.rida_fmt2 = 1;
4113 vha->d_id.b.domain = rptid_entry->port_id[2];
4114 vha->d_id.b.area = rptid_entry->port_id[1];
4115 vha->d_id.b.al_pa = rptid_entry->port_id[0];
4116
4117 ha->flags.n2n_ae = 1;
4118 spin_lock_irqsave(&ha->vport_slock, flags);
4119 qlt_update_vp_map(vha, SET_AL_PA);
4120 spin_unlock_irqrestore(&ha->vport_slock, flags);
4121
4122 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4123 fcport->scan_state = QLA_FCPORT_SCAN;
4124 fcport->n2n_flag = 0;
4125 }
4126
4127 fcport = qla2x00_find_fcport_by_wwpn(vha,
4128 rptid_entry->u.f2.port_name, 1);
4129
4130 if (fcport) {
4131 fcport->login_retry = vha->hw->login_retry_count;
4132 fcport->plogi_nack_done_deadline = jiffies + HZ;
4133 fcport->scan_state = QLA_FCPORT_FOUND;
4134 fcport->keep_nport_handle = 1;
4135 fcport->n2n_flag = 1;
4136 fcport->d_id.b.domain =
4137 rptid_entry->u.f2.remote_nport_id[2];
4138 fcport->d_id.b.area =
4139 rptid_entry->u.f2.remote_nport_id[1];
4140 fcport->d_id.b.al_pa =
4141 rptid_entry->u.f2.remote_nport_id[0];
4142 }
4143 }
4144 }
4145
4146 /*
4147 * qla24xx_modify_vp_config
4148 * Change VP configuration for vha
4149 *
4150 * Input:
4151 * vha = adapter block pointer.
4152 *
4153 * Returns:
4154 * qla2xxx local function return status code.
4155 *
4156 * Context:
4157 * Kernel context.
4158 */
4159 int
qla24xx_modify_vp_config(scsi_qla_host_t * vha)4160 qla24xx_modify_vp_config(scsi_qla_host_t *vha)
4161 {
4162 int rval;
4163 struct vp_config_entry_24xx *vpmod;
4164 dma_addr_t vpmod_dma;
4165 struct qla_hw_data *ha = vha->hw;
4166 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4167
4168 /* This can be called by the parent */
4169
4170 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
4171 "Entered %s.\n", __func__);
4172
4173 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
4174 if (!vpmod) {
4175 ql_log(ql_log_warn, vha, 0x10bc,
4176 "Failed to allocate modify VP IOCB.\n");
4177 return QLA_MEMORY_ALLOC_FAILED;
4178 }
4179
4180 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
4181 vpmod->entry_count = 1;
4182 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
4183 vpmod->vp_count = 1;
4184 vpmod->vp_index1 = vha->vp_idx;
4185 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
4186
4187 qlt_modify_vp_config(vha, vpmod);
4188
4189 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
4190 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
4191 vpmod->entry_count = 1;
4192
4193 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
4194 if (rval != QLA_SUCCESS) {
4195 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
4196 "Failed to issue VP config IOCB (%x).\n", rval);
4197 } else if (vpmod->comp_status != 0) {
4198 ql_dbg(ql_dbg_mbx, vha, 0x10be,
4199 "Failed to complete IOCB -- error status (%x).\n",
4200 vpmod->comp_status);
4201 rval = QLA_FUNCTION_FAILED;
4202 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
4203 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
4204 "Failed to complete IOCB -- completion status (%x).\n",
4205 le16_to_cpu(vpmod->comp_status));
4206 rval = QLA_FUNCTION_FAILED;
4207 } else {
4208 /* EMPTY */
4209 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
4210 "Done %s.\n", __func__);
4211 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
4212 }
4213 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
4214
4215 return rval;
4216 }
4217
4218 /*
4219 * qla2x00_send_change_request
4220 * Receive or disable RSCN request from fabric controller
4221 *
4222 * Input:
4223 * ha = adapter block pointer
4224 * format = registration format:
4225 * 0 - Reserved
4226 * 1 - Fabric detected registration
4227 * 2 - N_port detected registration
4228 * 3 - Full registration
4229 * FF - clear registration
4230 * vp_idx = Virtual port index
4231 *
4232 * Returns:
4233 * qla2x00 local function return status code.
4234 *
4235 * Context:
4236 * Kernel Context
4237 */
4238
4239 int
qla2x00_send_change_request(scsi_qla_host_t * vha,uint16_t format,uint16_t vp_idx)4240 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
4241 uint16_t vp_idx)
4242 {
4243 int rval;
4244 mbx_cmd_t mc;
4245 mbx_cmd_t *mcp = &mc;
4246
4247 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
4248 "Entered %s.\n", __func__);
4249
4250 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
4251 mcp->mb[1] = format;
4252 mcp->mb[9] = vp_idx;
4253 mcp->out_mb = MBX_9|MBX_1|MBX_0;
4254 mcp->in_mb = MBX_0|MBX_1;
4255 mcp->tov = MBX_TOV_SECONDS;
4256 mcp->flags = 0;
4257 rval = qla2x00_mailbox_command(vha, mcp);
4258
4259 if (rval == QLA_SUCCESS) {
4260 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
4261 rval = BIT_1;
4262 }
4263 } else
4264 rval = BIT_1;
4265
4266 return rval;
4267 }
4268
4269 int
qla2x00_dump_ram(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t addr,uint32_t size)4270 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
4271 uint32_t size)
4272 {
4273 int rval;
4274 mbx_cmd_t mc;
4275 mbx_cmd_t *mcp = &mc;
4276
4277 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
4278 "Entered %s.\n", __func__);
4279
4280 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
4281 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4282 mcp->mb[8] = MSW(addr);
4283 mcp->out_mb = MBX_8|MBX_0;
4284 } else {
4285 mcp->mb[0] = MBC_DUMP_RISC_RAM;
4286 mcp->out_mb = MBX_0;
4287 }
4288 mcp->mb[1] = LSW(addr);
4289 mcp->mb[2] = MSW(req_dma);
4290 mcp->mb[3] = LSW(req_dma);
4291 mcp->mb[6] = MSW(MSD(req_dma));
4292 mcp->mb[7] = LSW(MSD(req_dma));
4293 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
4294 if (IS_FWI2_CAPABLE(vha->hw)) {
4295 mcp->mb[4] = MSW(size);
4296 mcp->mb[5] = LSW(size);
4297 mcp->out_mb |= MBX_5|MBX_4;
4298 } else {
4299 mcp->mb[4] = LSW(size);
4300 mcp->out_mb |= MBX_4;
4301 }
4302
4303 mcp->in_mb = MBX_0;
4304 mcp->tov = MBX_TOV_SECONDS;
4305 mcp->flags = 0;
4306 rval = qla2x00_mailbox_command(vha, mcp);
4307
4308 if (rval != QLA_SUCCESS) {
4309 ql_dbg(ql_dbg_mbx, vha, 0x1008,
4310 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4311 } else {
4312 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
4313 "Done %s.\n", __func__);
4314 }
4315
4316 return rval;
4317 }
4318 /* 84XX Support **************************************************************/
4319
4320 struct cs84xx_mgmt_cmd {
4321 union {
4322 struct verify_chip_entry_84xx req;
4323 struct verify_chip_rsp_84xx rsp;
4324 } p;
4325 };
4326
4327 int
qla84xx_verify_chip(struct scsi_qla_host * vha,uint16_t * status)4328 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4329 {
4330 int rval, retry;
4331 struct cs84xx_mgmt_cmd *mn;
4332 dma_addr_t mn_dma;
4333 uint16_t options;
4334 unsigned long flags;
4335 struct qla_hw_data *ha = vha->hw;
4336
4337 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4338 "Entered %s.\n", __func__);
4339
4340 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4341 if (mn == NULL) {
4342 return QLA_MEMORY_ALLOC_FAILED;
4343 }
4344
4345 /* Force Update? */
4346 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4347 /* Diagnostic firmware? */
4348 /* options |= MENLO_DIAG_FW; */
4349 /* We update the firmware with only one data sequence. */
4350 options |= VCO_END_OF_DATA;
4351
4352 do {
4353 retry = 0;
4354 memset(mn, 0, sizeof(*mn));
4355 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4356 mn->p.req.entry_count = 1;
4357 mn->p.req.options = cpu_to_le16(options);
4358
4359 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4360 "Dump of Verify Request.\n");
4361 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4362 mn, sizeof(*mn));
4363
4364 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4365 if (rval != QLA_SUCCESS) {
4366 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4367 "Failed to issue verify IOCB (%x).\n", rval);
4368 goto verify_done;
4369 }
4370
4371 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4372 "Dump of Verify Response.\n");
4373 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4374 mn, sizeof(*mn));
4375
4376 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4377 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4378 le16_to_cpu(mn->p.rsp.failure_code) : 0;
4379 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
4380 "cs=%x fc=%x.\n", status[0], status[1]);
4381
4382 if (status[0] != CS_COMPLETE) {
4383 rval = QLA_FUNCTION_FAILED;
4384 if (!(options & VCO_DONT_UPDATE_FW)) {
4385 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4386 "Firmware update failed. Retrying "
4387 "without update firmware.\n");
4388 options |= VCO_DONT_UPDATE_FW;
4389 options &= ~VCO_FORCE_UPDATE;
4390 retry = 1;
4391 }
4392 } else {
4393 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
4394 "Firmware updated to %x.\n",
4395 le32_to_cpu(mn->p.rsp.fw_ver));
4396
4397 /* NOTE: we only update OP firmware. */
4398 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4399 ha->cs84xx->op_fw_version =
4400 le32_to_cpu(mn->p.rsp.fw_ver);
4401 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4402 flags);
4403 }
4404 } while (retry);
4405
4406 verify_done:
4407 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4408
4409 if (rval != QLA_SUCCESS) {
4410 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4411 "Failed=%x.\n", rval);
4412 } else {
4413 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4414 "Done %s.\n", __func__);
4415 }
4416
4417 return rval;
4418 }
4419
4420 int
qla25xx_init_req_que(struct scsi_qla_host * vha,struct req_que * req)4421 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
4422 {
4423 int rval;
4424 unsigned long flags;
4425 mbx_cmd_t mc;
4426 mbx_cmd_t *mcp = &mc;
4427 struct qla_hw_data *ha = vha->hw;
4428
4429 if (!ha->flags.fw_started)
4430 return QLA_SUCCESS;
4431
4432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4433 "Entered %s.\n", __func__);
4434
4435 if (IS_SHADOW_REG_CAPABLE(ha))
4436 req->options |= BIT_13;
4437
4438 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
4439 mcp->mb[1] = req->options;
4440 mcp->mb[2] = MSW(LSD(req->dma));
4441 mcp->mb[3] = LSW(LSD(req->dma));
4442 mcp->mb[6] = MSW(MSD(req->dma));
4443 mcp->mb[7] = LSW(MSD(req->dma));
4444 mcp->mb[5] = req->length;
4445 if (req->rsp)
4446 mcp->mb[10] = req->rsp->id;
4447 mcp->mb[12] = req->qos;
4448 mcp->mb[11] = req->vp_idx;
4449 mcp->mb[13] = req->rid;
4450 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4451 mcp->mb[15] = 0;
4452
4453 mcp->mb[4] = req->id;
4454 /* que in ptr index */
4455 mcp->mb[8] = 0;
4456 /* que out ptr index */
4457 mcp->mb[9] = *req->out_ptr = 0;
4458 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4459 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4460 mcp->in_mb = MBX_0;
4461 mcp->flags = MBX_DMA_OUT;
4462 mcp->tov = MBX_TOV_SECONDS * 2;
4463
4464 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4465 IS_QLA28XX(ha))
4466 mcp->in_mb |= MBX_1;
4467 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4468 mcp->out_mb |= MBX_15;
4469 /* debug q create issue in SR-IOV */
4470 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4471 }
4472
4473 spin_lock_irqsave(&ha->hardware_lock, flags);
4474 if (!(req->options & BIT_0)) {
4475 wrt_reg_dword(req->req_q_in, 0);
4476 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4477 wrt_reg_dword(req->req_q_out, 0);
4478 }
4479 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4480
4481 rval = qla2x00_mailbox_command(vha, mcp);
4482 if (rval != QLA_SUCCESS) {
4483 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4484 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4485 } else {
4486 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4487 "Done %s.\n", __func__);
4488 }
4489
4490 return rval;
4491 }
4492
4493 int
qla25xx_init_rsp_que(struct scsi_qla_host * vha,struct rsp_que * rsp)4494 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
4495 {
4496 int rval;
4497 unsigned long flags;
4498 mbx_cmd_t mc;
4499 mbx_cmd_t *mcp = &mc;
4500 struct qla_hw_data *ha = vha->hw;
4501
4502 if (!ha->flags.fw_started)
4503 return QLA_SUCCESS;
4504
4505 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4506 "Entered %s.\n", __func__);
4507
4508 if (IS_SHADOW_REG_CAPABLE(ha))
4509 rsp->options |= BIT_13;
4510
4511 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
4512 mcp->mb[1] = rsp->options;
4513 mcp->mb[2] = MSW(LSD(rsp->dma));
4514 mcp->mb[3] = LSW(LSD(rsp->dma));
4515 mcp->mb[6] = MSW(MSD(rsp->dma));
4516 mcp->mb[7] = LSW(MSD(rsp->dma));
4517 mcp->mb[5] = rsp->length;
4518 mcp->mb[14] = rsp->msix->entry;
4519 mcp->mb[13] = rsp->rid;
4520 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4521 mcp->mb[15] = 0;
4522
4523 mcp->mb[4] = rsp->id;
4524 /* que in ptr index */
4525 mcp->mb[8] = *rsp->in_ptr = 0;
4526 /* que out ptr index */
4527 mcp->mb[9] = 0;
4528 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
4529 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4530 mcp->in_mb = MBX_0;
4531 mcp->flags = MBX_DMA_OUT;
4532 mcp->tov = MBX_TOV_SECONDS * 2;
4533
4534 if (IS_QLA81XX(ha)) {
4535 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4536 mcp->in_mb |= MBX_1;
4537 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4538 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4539 mcp->in_mb |= MBX_1;
4540 /* debug q create issue in SR-IOV */
4541 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4542 }
4543
4544 spin_lock_irqsave(&ha->hardware_lock, flags);
4545 if (!(rsp->options & BIT_0)) {
4546 wrt_reg_dword(rsp->rsp_q_out, 0);
4547 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4548 wrt_reg_dword(rsp->rsp_q_in, 0);
4549 }
4550
4551 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4552
4553 rval = qla2x00_mailbox_command(vha, mcp);
4554 if (rval != QLA_SUCCESS) {
4555 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4556 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4557 } else {
4558 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4559 "Done %s.\n", __func__);
4560 }
4561
4562 return rval;
4563 }
4564
4565 int
qla81xx_idc_ack(scsi_qla_host_t * vha,uint16_t * mb)4566 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4567 {
4568 int rval;
4569 mbx_cmd_t mc;
4570 mbx_cmd_t *mcp = &mc;
4571
4572 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4573 "Entered %s.\n", __func__);
4574
4575 mcp->mb[0] = MBC_IDC_ACK;
4576 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4577 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4578 mcp->in_mb = MBX_0;
4579 mcp->tov = MBX_TOV_SECONDS;
4580 mcp->flags = 0;
4581 rval = qla2x00_mailbox_command(vha, mcp);
4582
4583 if (rval != QLA_SUCCESS) {
4584 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4585 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4586 } else {
4587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4588 "Done %s.\n", __func__);
4589 }
4590
4591 return rval;
4592 }
4593
4594 int
qla81xx_fac_get_sector_size(scsi_qla_host_t * vha,uint32_t * sector_size)4595 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4596 {
4597 int rval;
4598 mbx_cmd_t mc;
4599 mbx_cmd_t *mcp = &mc;
4600
4601 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4602 "Entered %s.\n", __func__);
4603
4604 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4605 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4606 return QLA_FUNCTION_FAILED;
4607
4608 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4609 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4610 mcp->out_mb = MBX_1|MBX_0;
4611 mcp->in_mb = MBX_1|MBX_0;
4612 mcp->tov = MBX_TOV_SECONDS;
4613 mcp->flags = 0;
4614 rval = qla2x00_mailbox_command(vha, mcp);
4615
4616 if (rval != QLA_SUCCESS) {
4617 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4618 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4619 rval, mcp->mb[0], mcp->mb[1]);
4620 } else {
4621 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4622 "Done %s.\n", __func__);
4623 *sector_size = mcp->mb[1];
4624 }
4625
4626 return rval;
4627 }
4628
4629 int
qla81xx_fac_do_write_enable(scsi_qla_host_t * vha,int enable)4630 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4631 {
4632 int rval;
4633 mbx_cmd_t mc;
4634 mbx_cmd_t *mcp = &mc;
4635
4636 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4637 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4638 return QLA_FUNCTION_FAILED;
4639
4640 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4641 "Entered %s.\n", __func__);
4642
4643 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4644 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4645 FAC_OPT_CMD_WRITE_PROTECT;
4646 mcp->out_mb = MBX_1|MBX_0;
4647 mcp->in_mb = MBX_1|MBX_0;
4648 mcp->tov = MBX_TOV_SECONDS;
4649 mcp->flags = 0;
4650 rval = qla2x00_mailbox_command(vha, mcp);
4651
4652 if (rval != QLA_SUCCESS) {
4653 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4654 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4655 rval, mcp->mb[0], mcp->mb[1]);
4656 } else {
4657 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4658 "Done %s.\n", __func__);
4659 }
4660
4661 return rval;
4662 }
4663
4664 int
qla81xx_fac_erase_sector(scsi_qla_host_t * vha,uint32_t start,uint32_t finish)4665 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4666 {
4667 int rval;
4668 mbx_cmd_t mc;
4669 mbx_cmd_t *mcp = &mc;
4670
4671 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4672 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4673 return QLA_FUNCTION_FAILED;
4674
4675 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4676 "Entered %s.\n", __func__);
4677
4678 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4679 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4680 mcp->mb[2] = LSW(start);
4681 mcp->mb[3] = MSW(start);
4682 mcp->mb[4] = LSW(finish);
4683 mcp->mb[5] = MSW(finish);
4684 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4685 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4686 mcp->tov = MBX_TOV_SECONDS;
4687 mcp->flags = 0;
4688 rval = qla2x00_mailbox_command(vha, mcp);
4689
4690 if (rval != QLA_SUCCESS) {
4691 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4692 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4693 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4694 } else {
4695 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4696 "Done %s.\n", __func__);
4697 }
4698
4699 return rval;
4700 }
4701
4702 int
qla81xx_fac_semaphore_access(scsi_qla_host_t * vha,int lock)4703 qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
4704 {
4705 int rval = QLA_SUCCESS;
4706 mbx_cmd_t mc;
4707 mbx_cmd_t *mcp = &mc;
4708 struct qla_hw_data *ha = vha->hw;
4709
4710 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
4711 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4712 return rval;
4713
4714 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4715 "Entered %s.\n", __func__);
4716
4717 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4718 mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
4719 FAC_OPT_CMD_UNLOCK_SEMAPHORE);
4720 mcp->out_mb = MBX_1|MBX_0;
4721 mcp->in_mb = MBX_1|MBX_0;
4722 mcp->tov = MBX_TOV_SECONDS;
4723 mcp->flags = 0;
4724 rval = qla2x00_mailbox_command(vha, mcp);
4725
4726 if (rval != QLA_SUCCESS) {
4727 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4728 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4729 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4730 } else {
4731 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4732 "Done %s.\n", __func__);
4733 }
4734
4735 return rval;
4736 }
4737
4738 int
qla81xx_restart_mpi_firmware(scsi_qla_host_t * vha)4739 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4740 {
4741 int rval = 0;
4742 mbx_cmd_t mc;
4743 mbx_cmd_t *mcp = &mc;
4744
4745 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4746 "Entered %s.\n", __func__);
4747
4748 mcp->mb[0] = MBC_RESTART_MPI_FW;
4749 mcp->out_mb = MBX_0;
4750 mcp->in_mb = MBX_0|MBX_1;
4751 mcp->tov = MBX_TOV_SECONDS;
4752 mcp->flags = 0;
4753 rval = qla2x00_mailbox_command(vha, mcp);
4754
4755 if (rval != QLA_SUCCESS) {
4756 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4757 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4758 rval, mcp->mb[0], mcp->mb[1]);
4759 } else {
4760 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4761 "Done %s.\n", __func__);
4762 }
4763
4764 return rval;
4765 }
4766
4767 int
qla82xx_set_driver_version(scsi_qla_host_t * vha,char * version)4768 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4769 {
4770 int rval;
4771 mbx_cmd_t mc;
4772 mbx_cmd_t *mcp = &mc;
4773 int i;
4774 int len;
4775 __le16 *str;
4776 struct qla_hw_data *ha = vha->hw;
4777
4778 if (!IS_P3P_TYPE(ha))
4779 return QLA_FUNCTION_FAILED;
4780
4781 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4782 "Entered %s.\n", __func__);
4783
4784 str = (__force __le16 *)version;
4785 len = strlen(version);
4786
4787 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4788 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4789 mcp->out_mb = MBX_1|MBX_0;
4790 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4791 mcp->mb[i] = le16_to_cpup(str);
4792 mcp->out_mb |= 1<<i;
4793 }
4794 for (; i < 16; i++) {
4795 mcp->mb[i] = 0;
4796 mcp->out_mb |= 1<<i;
4797 }
4798 mcp->in_mb = MBX_1|MBX_0;
4799 mcp->tov = MBX_TOV_SECONDS;
4800 mcp->flags = 0;
4801 rval = qla2x00_mailbox_command(vha, mcp);
4802
4803 if (rval != QLA_SUCCESS) {
4804 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4805 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4806 } else {
4807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4808 "Done %s.\n", __func__);
4809 }
4810
4811 return rval;
4812 }
4813
4814 int
qla25xx_set_driver_version(scsi_qla_host_t * vha,char * version)4815 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4816 {
4817 int rval;
4818 mbx_cmd_t mc;
4819 mbx_cmd_t *mcp = &mc;
4820 int len;
4821 uint16_t dwlen;
4822 uint8_t *str;
4823 dma_addr_t str_dma;
4824 struct qla_hw_data *ha = vha->hw;
4825
4826 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4827 IS_P3P_TYPE(ha))
4828 return QLA_FUNCTION_FAILED;
4829
4830 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4831 "Entered %s.\n", __func__);
4832
4833 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4834 if (!str) {
4835 ql_log(ql_log_warn, vha, 0x117f,
4836 "Failed to allocate driver version param.\n");
4837 return QLA_MEMORY_ALLOC_FAILED;
4838 }
4839
4840 memcpy(str, "\x7\x3\x11\x0", 4);
4841 dwlen = str[0];
4842 len = dwlen * 4 - 4;
4843 memset(str + 4, 0, len);
4844 if (len > strlen(version))
4845 len = strlen(version);
4846 memcpy(str + 4, version, len);
4847
4848 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4849 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4850 mcp->mb[2] = MSW(LSD(str_dma));
4851 mcp->mb[3] = LSW(LSD(str_dma));
4852 mcp->mb[6] = MSW(MSD(str_dma));
4853 mcp->mb[7] = LSW(MSD(str_dma));
4854 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4855 mcp->in_mb = MBX_1|MBX_0;
4856 mcp->tov = MBX_TOV_SECONDS;
4857 mcp->flags = 0;
4858 rval = qla2x00_mailbox_command(vha, mcp);
4859
4860 if (rval != QLA_SUCCESS) {
4861 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4862 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4863 } else {
4864 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4865 "Done %s.\n", __func__);
4866 }
4867
4868 dma_pool_free(ha->s_dma_pool, str, str_dma);
4869
4870 return rval;
4871 }
4872
4873 int
qla24xx_get_port_login_templ(scsi_qla_host_t * vha,dma_addr_t buf_dma,void * buf,uint16_t bufsiz)4874 qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma,
4875 void *buf, uint16_t bufsiz)
4876 {
4877 int rval, i;
4878 mbx_cmd_t mc;
4879 mbx_cmd_t *mcp = &mc;
4880 uint32_t *bp;
4881
4882 if (!IS_FWI2_CAPABLE(vha->hw))
4883 return QLA_FUNCTION_FAILED;
4884
4885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4886 "Entered %s.\n", __func__);
4887
4888 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4889 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8;
4890 mcp->mb[2] = MSW(buf_dma);
4891 mcp->mb[3] = LSW(buf_dma);
4892 mcp->mb[6] = MSW(MSD(buf_dma));
4893 mcp->mb[7] = LSW(MSD(buf_dma));
4894 mcp->mb[8] = bufsiz/4;
4895 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4896 mcp->in_mb = MBX_1|MBX_0;
4897 mcp->tov = MBX_TOV_SECONDS;
4898 mcp->flags = 0;
4899 rval = qla2x00_mailbox_command(vha, mcp);
4900
4901 if (rval != QLA_SUCCESS) {
4902 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4903 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4904 } else {
4905 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4906 "Done %s.\n", __func__);
4907 bp = (uint32_t *) buf;
4908 for (i = 0; i < (bufsiz-4)/4; i++, bp++)
4909 *bp = le32_to_cpu((__force __le32)*bp);
4910 }
4911
4912 return rval;
4913 }
4914
4915 #define PUREX_CMD_COUNT 2
4916 int
qla25xx_set_els_cmds_supported(scsi_qla_host_t * vha)4917 qla25xx_set_els_cmds_supported(scsi_qla_host_t *vha)
4918 {
4919 int rval;
4920 mbx_cmd_t mc;
4921 mbx_cmd_t *mcp = &mc;
4922 uint8_t *els_cmd_map;
4923 dma_addr_t els_cmd_map_dma;
4924 uint8_t cmd_opcode[PUREX_CMD_COUNT];
4925 uint8_t i, index, purex_bit;
4926 struct qla_hw_data *ha = vha->hw;
4927
4928 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha) &&
4929 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
4930 return QLA_SUCCESS;
4931
4932 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1197,
4933 "Entered %s.\n", __func__);
4934
4935 els_cmd_map = dma_alloc_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
4936 &els_cmd_map_dma, GFP_KERNEL);
4937 if (!els_cmd_map) {
4938 ql_log(ql_log_warn, vha, 0x7101,
4939 "Failed to allocate RDP els command param.\n");
4940 return QLA_MEMORY_ALLOC_FAILED;
4941 }
4942
4943 /* List of Purex ELS */
4944 cmd_opcode[0] = ELS_FPIN;
4945 cmd_opcode[1] = ELS_RDP;
4946
4947 for (i = 0; i < PUREX_CMD_COUNT; i++) {
4948 index = cmd_opcode[i] / 8;
4949 purex_bit = cmd_opcode[i] % 8;
4950 els_cmd_map[index] |= 1 << purex_bit;
4951 }
4952
4953 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4954 mcp->mb[1] = RNID_TYPE_ELS_CMD << 8;
4955 mcp->mb[2] = MSW(LSD(els_cmd_map_dma));
4956 mcp->mb[3] = LSW(LSD(els_cmd_map_dma));
4957 mcp->mb[6] = MSW(MSD(els_cmd_map_dma));
4958 mcp->mb[7] = LSW(MSD(els_cmd_map_dma));
4959 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4960 mcp->in_mb = MBX_1|MBX_0;
4961 mcp->tov = MBX_TOV_SECONDS;
4962 mcp->flags = MBX_DMA_OUT;
4963 mcp->buf_size = ELS_CMD_MAP_SIZE;
4964 rval = qla2x00_mailbox_command(vha, mcp);
4965
4966 if (rval != QLA_SUCCESS) {
4967 ql_dbg(ql_dbg_mbx, vha, 0x118d,
4968 "Failed=%x (%x,%x).\n", rval, mcp->mb[0], mcp->mb[1]);
4969 } else {
4970 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
4971 "Done %s.\n", __func__);
4972 }
4973
4974 dma_free_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
4975 els_cmd_map, els_cmd_map_dma);
4976
4977 return rval;
4978 }
4979
4980 static int
qla2x00_read_asic_temperature(scsi_qla_host_t * vha,uint16_t * temp)4981 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4982 {
4983 int rval;
4984 mbx_cmd_t mc;
4985 mbx_cmd_t *mcp = &mc;
4986
4987 if (!IS_FWI2_CAPABLE(vha->hw))
4988 return QLA_FUNCTION_FAILED;
4989
4990 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4991 "Entered %s.\n", __func__);
4992
4993 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4994 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4995 mcp->out_mb = MBX_1|MBX_0;
4996 mcp->in_mb = MBX_1|MBX_0;
4997 mcp->tov = MBX_TOV_SECONDS;
4998 mcp->flags = 0;
4999 rval = qla2x00_mailbox_command(vha, mcp);
5000 *temp = mcp->mb[1];
5001
5002 if (rval != QLA_SUCCESS) {
5003 ql_dbg(ql_dbg_mbx, vha, 0x115a,
5004 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
5005 } else {
5006 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
5007 "Done %s.\n", __func__);
5008 }
5009
5010 return rval;
5011 }
5012
5013 int
qla2x00_read_sfp(scsi_qla_host_t * vha,dma_addr_t sfp_dma,uint8_t * sfp,uint16_t dev,uint16_t off,uint16_t len,uint16_t opt)5014 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
5015 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
5016 {
5017 int rval;
5018 mbx_cmd_t mc;
5019 mbx_cmd_t *mcp = &mc;
5020 struct qla_hw_data *ha = vha->hw;
5021
5022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
5023 "Entered %s.\n", __func__);
5024
5025 if (!IS_FWI2_CAPABLE(ha))
5026 return QLA_FUNCTION_FAILED;
5027
5028 if (len == 1)
5029 opt |= BIT_0;
5030
5031 mcp->mb[0] = MBC_READ_SFP;
5032 mcp->mb[1] = dev;
5033 mcp->mb[2] = MSW(LSD(sfp_dma));
5034 mcp->mb[3] = LSW(LSD(sfp_dma));
5035 mcp->mb[6] = MSW(MSD(sfp_dma));
5036 mcp->mb[7] = LSW(MSD(sfp_dma));
5037 mcp->mb[8] = len;
5038 mcp->mb[9] = off;
5039 mcp->mb[10] = opt;
5040 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5041 mcp->in_mb = MBX_1|MBX_0;
5042 mcp->tov = MBX_TOV_SECONDS;
5043 mcp->flags = 0;
5044 rval = qla2x00_mailbox_command(vha, mcp);
5045
5046 if (opt & BIT_0)
5047 *sfp = mcp->mb[1];
5048
5049 if (rval != QLA_SUCCESS) {
5050 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
5051 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5052 if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
5053 /* sfp is not there */
5054 rval = QLA_INTERFACE_ERROR;
5055 }
5056 } else {
5057 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
5058 "Done %s.\n", __func__);
5059 }
5060
5061 return rval;
5062 }
5063
5064 int
qla2x00_write_sfp(scsi_qla_host_t * vha,dma_addr_t sfp_dma,uint8_t * sfp,uint16_t dev,uint16_t off,uint16_t len,uint16_t opt)5065 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
5066 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
5067 {
5068 int rval;
5069 mbx_cmd_t mc;
5070 mbx_cmd_t *mcp = &mc;
5071 struct qla_hw_data *ha = vha->hw;
5072
5073 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
5074 "Entered %s.\n", __func__);
5075
5076 if (!IS_FWI2_CAPABLE(ha))
5077 return QLA_FUNCTION_FAILED;
5078
5079 if (len == 1)
5080 opt |= BIT_0;
5081
5082 if (opt & BIT_0)
5083 len = *sfp;
5084
5085 mcp->mb[0] = MBC_WRITE_SFP;
5086 mcp->mb[1] = dev;
5087 mcp->mb[2] = MSW(LSD(sfp_dma));
5088 mcp->mb[3] = LSW(LSD(sfp_dma));
5089 mcp->mb[6] = MSW(MSD(sfp_dma));
5090 mcp->mb[7] = LSW(MSD(sfp_dma));
5091 mcp->mb[8] = len;
5092 mcp->mb[9] = off;
5093 mcp->mb[10] = opt;
5094 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5095 mcp->in_mb = MBX_1|MBX_0;
5096 mcp->tov = MBX_TOV_SECONDS;
5097 mcp->flags = 0;
5098 rval = qla2x00_mailbox_command(vha, mcp);
5099
5100 if (rval != QLA_SUCCESS) {
5101 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
5102 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5103 } else {
5104 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
5105 "Done %s.\n", __func__);
5106 }
5107
5108 return rval;
5109 }
5110
5111 int
qla2x00_get_xgmac_stats(scsi_qla_host_t * vha,dma_addr_t stats_dma,uint16_t size_in_bytes,uint16_t * actual_size)5112 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
5113 uint16_t size_in_bytes, uint16_t *actual_size)
5114 {
5115 int rval;
5116 mbx_cmd_t mc;
5117 mbx_cmd_t *mcp = &mc;
5118
5119 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
5120 "Entered %s.\n", __func__);
5121
5122 if (!IS_CNA_CAPABLE(vha->hw))
5123 return QLA_FUNCTION_FAILED;
5124
5125 mcp->mb[0] = MBC_GET_XGMAC_STATS;
5126 mcp->mb[2] = MSW(stats_dma);
5127 mcp->mb[3] = LSW(stats_dma);
5128 mcp->mb[6] = MSW(MSD(stats_dma));
5129 mcp->mb[7] = LSW(MSD(stats_dma));
5130 mcp->mb[8] = size_in_bytes >> 2;
5131 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
5132 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5133 mcp->tov = MBX_TOV_SECONDS;
5134 mcp->flags = 0;
5135 rval = qla2x00_mailbox_command(vha, mcp);
5136
5137 if (rval != QLA_SUCCESS) {
5138 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
5139 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
5140 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
5141 } else {
5142 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
5143 "Done %s.\n", __func__);
5144
5145
5146 *actual_size = mcp->mb[2] << 2;
5147 }
5148
5149 return rval;
5150 }
5151
5152 int
qla2x00_get_dcbx_params(scsi_qla_host_t * vha,dma_addr_t tlv_dma,uint16_t size)5153 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
5154 uint16_t size)
5155 {
5156 int rval;
5157 mbx_cmd_t mc;
5158 mbx_cmd_t *mcp = &mc;
5159
5160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
5161 "Entered %s.\n", __func__);
5162
5163 if (!IS_CNA_CAPABLE(vha->hw))
5164 return QLA_FUNCTION_FAILED;
5165
5166 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
5167 mcp->mb[1] = 0;
5168 mcp->mb[2] = MSW(tlv_dma);
5169 mcp->mb[3] = LSW(tlv_dma);
5170 mcp->mb[6] = MSW(MSD(tlv_dma));
5171 mcp->mb[7] = LSW(MSD(tlv_dma));
5172 mcp->mb[8] = size;
5173 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5174 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5175 mcp->tov = MBX_TOV_SECONDS;
5176 mcp->flags = 0;
5177 rval = qla2x00_mailbox_command(vha, mcp);
5178
5179 if (rval != QLA_SUCCESS) {
5180 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
5181 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
5182 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
5183 } else {
5184 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
5185 "Done %s.\n", __func__);
5186 }
5187
5188 return rval;
5189 }
5190
5191 int
qla2x00_read_ram_word(scsi_qla_host_t * vha,uint32_t risc_addr,uint32_t * data)5192 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
5193 {
5194 int rval;
5195 mbx_cmd_t mc;
5196 mbx_cmd_t *mcp = &mc;
5197
5198 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
5199 "Entered %s.\n", __func__);
5200
5201 if (!IS_FWI2_CAPABLE(vha->hw))
5202 return QLA_FUNCTION_FAILED;
5203
5204 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
5205 mcp->mb[1] = LSW(risc_addr);
5206 mcp->mb[8] = MSW(risc_addr);
5207 mcp->out_mb = MBX_8|MBX_1|MBX_0;
5208 mcp->in_mb = MBX_3|MBX_2|MBX_0;
5209 mcp->tov = MBX_TOV_SECONDS;
5210 mcp->flags = 0;
5211 rval = qla2x00_mailbox_command(vha, mcp);
5212 if (rval != QLA_SUCCESS) {
5213 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
5214 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5215 } else {
5216 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
5217 "Done %s.\n", __func__);
5218 *data = mcp->mb[3] << 16 | mcp->mb[2];
5219 }
5220
5221 return rval;
5222 }
5223
5224 int
qla2x00_loopback_test(scsi_qla_host_t * vha,struct msg_echo_lb * mreq,uint16_t * mresp)5225 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5226 uint16_t *mresp)
5227 {
5228 int rval;
5229 mbx_cmd_t mc;
5230 mbx_cmd_t *mcp = &mc;
5231
5232 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
5233 "Entered %s.\n", __func__);
5234
5235 memset(mcp->mb, 0 , sizeof(mcp->mb));
5236 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
5237 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
5238
5239 /* transfer count */
5240 mcp->mb[10] = LSW(mreq->transfer_size);
5241 mcp->mb[11] = MSW(mreq->transfer_size);
5242
5243 /* send data address */
5244 mcp->mb[14] = LSW(mreq->send_dma);
5245 mcp->mb[15] = MSW(mreq->send_dma);
5246 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5247 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5248
5249 /* receive data address */
5250 mcp->mb[16] = LSW(mreq->rcv_dma);
5251 mcp->mb[17] = MSW(mreq->rcv_dma);
5252 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5253 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5254
5255 /* Iteration count */
5256 mcp->mb[18] = LSW(mreq->iteration_count);
5257 mcp->mb[19] = MSW(mreq->iteration_count);
5258
5259 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
5260 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
5261 if (IS_CNA_CAPABLE(vha->hw))
5262 mcp->out_mb |= MBX_2;
5263 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
5264
5265 mcp->buf_size = mreq->transfer_size;
5266 mcp->tov = MBX_TOV_SECONDS;
5267 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5268
5269 rval = qla2x00_mailbox_command(vha, mcp);
5270
5271 if (rval != QLA_SUCCESS) {
5272 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
5273 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
5274 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
5275 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
5276 } else {
5277 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
5278 "Done %s.\n", __func__);
5279 }
5280
5281 /* Copy mailbox information */
5282 memcpy( mresp, mcp->mb, 64);
5283 return rval;
5284 }
5285
5286 int
qla2x00_echo_test(scsi_qla_host_t * vha,struct msg_echo_lb * mreq,uint16_t * mresp)5287 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5288 uint16_t *mresp)
5289 {
5290 int rval;
5291 mbx_cmd_t mc;
5292 mbx_cmd_t *mcp = &mc;
5293 struct qla_hw_data *ha = vha->hw;
5294
5295 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
5296 "Entered %s.\n", __func__);
5297
5298 memset(mcp->mb, 0 , sizeof(mcp->mb));
5299 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
5300 /* BIT_6 specifies 64bit address */
5301 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
5302 if (IS_CNA_CAPABLE(ha)) {
5303 mcp->mb[2] = vha->fcoe_fcf_idx;
5304 }
5305 mcp->mb[16] = LSW(mreq->rcv_dma);
5306 mcp->mb[17] = MSW(mreq->rcv_dma);
5307 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5308 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5309
5310 mcp->mb[10] = LSW(mreq->transfer_size);
5311
5312 mcp->mb[14] = LSW(mreq->send_dma);
5313 mcp->mb[15] = MSW(mreq->send_dma);
5314 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5315 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5316
5317 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
5318 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
5319 if (IS_CNA_CAPABLE(ha))
5320 mcp->out_mb |= MBX_2;
5321
5322 mcp->in_mb = MBX_0;
5323 if (IS_CNA_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
5324 IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5325 mcp->in_mb |= MBX_1;
5326 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
5327 IS_QLA28XX(ha))
5328 mcp->in_mb |= MBX_3;
5329
5330 mcp->tov = MBX_TOV_SECONDS;
5331 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5332 mcp->buf_size = mreq->transfer_size;
5333
5334 rval = qla2x00_mailbox_command(vha, mcp);
5335
5336 if (rval != QLA_SUCCESS) {
5337 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
5338 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5339 rval, mcp->mb[0], mcp->mb[1]);
5340 } else {
5341 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
5342 "Done %s.\n", __func__);
5343 }
5344
5345 /* Copy mailbox information */
5346 memcpy(mresp, mcp->mb, 64);
5347 return rval;
5348 }
5349
5350 int
qla84xx_reset_chip(scsi_qla_host_t * vha,uint16_t enable_diagnostic)5351 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
5352 {
5353 int rval;
5354 mbx_cmd_t mc;
5355 mbx_cmd_t *mcp = &mc;
5356
5357 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
5358 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
5359
5360 mcp->mb[0] = MBC_ISP84XX_RESET;
5361 mcp->mb[1] = enable_diagnostic;
5362 mcp->out_mb = MBX_1|MBX_0;
5363 mcp->in_mb = MBX_1|MBX_0;
5364 mcp->tov = MBX_TOV_SECONDS;
5365 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5366 rval = qla2x00_mailbox_command(vha, mcp);
5367
5368 if (rval != QLA_SUCCESS)
5369 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
5370 else
5371 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
5372 "Done %s.\n", __func__);
5373
5374 return rval;
5375 }
5376
5377 int
qla2x00_write_ram_word(scsi_qla_host_t * vha,uint32_t risc_addr,uint32_t data)5378 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
5379 {
5380 int rval;
5381 mbx_cmd_t mc;
5382 mbx_cmd_t *mcp = &mc;
5383
5384 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
5385 "Entered %s.\n", __func__);
5386
5387 if (!IS_FWI2_CAPABLE(vha->hw))
5388 return QLA_FUNCTION_FAILED;
5389
5390 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
5391 mcp->mb[1] = LSW(risc_addr);
5392 mcp->mb[2] = LSW(data);
5393 mcp->mb[3] = MSW(data);
5394 mcp->mb[8] = MSW(risc_addr);
5395 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
5396 mcp->in_mb = MBX_1|MBX_0;
5397 mcp->tov = MBX_TOV_SECONDS;
5398 mcp->flags = 0;
5399 rval = qla2x00_mailbox_command(vha, mcp);
5400 if (rval != QLA_SUCCESS) {
5401 ql_dbg(ql_dbg_mbx, vha, 0x1101,
5402 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5403 rval, mcp->mb[0], mcp->mb[1]);
5404 } else {
5405 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5406 "Done %s.\n", __func__);
5407 }
5408
5409 return rval;
5410 }
5411
5412 int
qla81xx_write_mpi_register(scsi_qla_host_t * vha,uint16_t * mb)5413 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
5414 {
5415 int rval;
5416 uint32_t stat, timer;
5417 uint16_t mb0 = 0;
5418 struct qla_hw_data *ha = vha->hw;
5419 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5420
5421 rval = QLA_SUCCESS;
5422
5423 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
5424 "Entered %s.\n", __func__);
5425
5426 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5427
5428 /* Write the MBC data to the registers */
5429 wrt_reg_word(®->mailbox0, MBC_WRITE_MPI_REGISTER);
5430 wrt_reg_word(®->mailbox1, mb[0]);
5431 wrt_reg_word(®->mailbox2, mb[1]);
5432 wrt_reg_word(®->mailbox3, mb[2]);
5433 wrt_reg_word(®->mailbox4, mb[3]);
5434
5435 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT);
5436
5437 /* Poll for MBC interrupt */
5438 for (timer = 6000000; timer; timer--) {
5439 /* Check for pending interrupts. */
5440 stat = rd_reg_dword(®->host_status);
5441 if (stat & HSRX_RISC_INT) {
5442 stat &= 0xff;
5443
5444 if (stat == 0x1 || stat == 0x2 ||
5445 stat == 0x10 || stat == 0x11) {
5446 set_bit(MBX_INTERRUPT,
5447 &ha->mbx_cmd_flags);
5448 mb0 = rd_reg_word(®->mailbox0);
5449 wrt_reg_dword(®->hccr,
5450 HCCRX_CLR_RISC_INT);
5451 rd_reg_dword(®->hccr);
5452 break;
5453 }
5454 }
5455 udelay(5);
5456 }
5457
5458 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
5459 rval = mb0 & MBS_MASK;
5460 else
5461 rval = QLA_FUNCTION_FAILED;
5462
5463 if (rval != QLA_SUCCESS) {
5464 ql_dbg(ql_dbg_mbx, vha, 0x1104,
5465 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
5466 } else {
5467 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
5468 "Done %s.\n", __func__);
5469 }
5470
5471 return rval;
5472 }
5473
5474 /* Set the specified data rate */
5475 int
qla2x00_set_data_rate(scsi_qla_host_t * vha,uint16_t mode)5476 qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
5477 {
5478 int rval;
5479 mbx_cmd_t mc;
5480 mbx_cmd_t *mcp = &mc;
5481 struct qla_hw_data *ha = vha->hw;
5482 uint16_t val;
5483
5484 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5485 "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate,
5486 mode);
5487
5488 if (!IS_FWI2_CAPABLE(ha))
5489 return QLA_FUNCTION_FAILED;
5490
5491 memset(mcp, 0, sizeof(*mcp));
5492 switch (ha->set_data_rate) {
5493 case PORT_SPEED_AUTO:
5494 case PORT_SPEED_4GB:
5495 case PORT_SPEED_8GB:
5496 case PORT_SPEED_16GB:
5497 case PORT_SPEED_32GB:
5498 val = ha->set_data_rate;
5499 break;
5500 default:
5501 ql_log(ql_log_warn, vha, 0x1199,
5502 "Unrecognized speed setting:%d. Setting Autoneg\n",
5503 ha->set_data_rate);
5504 val = ha->set_data_rate = PORT_SPEED_AUTO;
5505 break;
5506 }
5507
5508 mcp->mb[0] = MBC_DATA_RATE;
5509 mcp->mb[1] = mode;
5510 mcp->mb[2] = val;
5511
5512 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5513 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5514 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5515 mcp->in_mb |= MBX_4|MBX_3;
5516 mcp->tov = MBX_TOV_SECONDS;
5517 mcp->flags = 0;
5518 rval = qla2x00_mailbox_command(vha, mcp);
5519 if (rval != QLA_SUCCESS) {
5520 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5521 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5522 } else {
5523 if (mcp->mb[1] != 0x7)
5524 ql_dbg(ql_dbg_mbx, vha, 0x1179,
5525 "Speed set:0x%x\n", mcp->mb[1]);
5526
5527 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5528 "Done %s.\n", __func__);
5529 }
5530
5531 return rval;
5532 }
5533
5534 int
qla2x00_get_data_rate(scsi_qla_host_t * vha)5535 qla2x00_get_data_rate(scsi_qla_host_t *vha)
5536 {
5537 int rval;
5538 mbx_cmd_t mc;
5539 mbx_cmd_t *mcp = &mc;
5540 struct qla_hw_data *ha = vha->hw;
5541
5542 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5543 "Entered %s.\n", __func__);
5544
5545 if (!IS_FWI2_CAPABLE(ha))
5546 return QLA_FUNCTION_FAILED;
5547
5548 mcp->mb[0] = MBC_DATA_RATE;
5549 mcp->mb[1] = QLA_GET_DATA_RATE;
5550 mcp->out_mb = MBX_1|MBX_0;
5551 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5552 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5553 mcp->in_mb |= MBX_3;
5554 mcp->tov = MBX_TOV_SECONDS;
5555 mcp->flags = 0;
5556 rval = qla2x00_mailbox_command(vha, mcp);
5557 if (rval != QLA_SUCCESS) {
5558 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5559 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5560 } else {
5561 if (mcp->mb[1] != 0x7)
5562 ha->link_data_rate = mcp->mb[1];
5563
5564 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
5565 if (mcp->mb[4] & BIT_0)
5566 ql_log(ql_log_info, vha, 0x11a2,
5567 "FEC=enabled (data rate).\n");
5568 }
5569
5570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5571 "Done %s.\n", __func__);
5572 if (mcp->mb[1] != 0x7)
5573 ha->link_data_rate = mcp->mb[1];
5574 }
5575
5576 return rval;
5577 }
5578
5579 int
qla81xx_get_port_config(scsi_qla_host_t * vha,uint16_t * mb)5580 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5581 {
5582 int rval;
5583 mbx_cmd_t mc;
5584 mbx_cmd_t *mcp = &mc;
5585 struct qla_hw_data *ha = vha->hw;
5586
5587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5588 "Entered %s.\n", __func__);
5589
5590 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5591 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5592 return QLA_FUNCTION_FAILED;
5593 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5594 mcp->out_mb = MBX_0;
5595 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5596 mcp->tov = MBX_TOV_SECONDS;
5597 mcp->flags = 0;
5598
5599 rval = qla2x00_mailbox_command(vha, mcp);
5600
5601 if (rval != QLA_SUCCESS) {
5602 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5603 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5604 } else {
5605 /* Copy all bits to preserve original value */
5606 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5607
5608 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5609 "Done %s.\n", __func__);
5610 }
5611 return rval;
5612 }
5613
5614 int
qla81xx_set_port_config(scsi_qla_host_t * vha,uint16_t * mb)5615 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5616 {
5617 int rval;
5618 mbx_cmd_t mc;
5619 mbx_cmd_t *mcp = &mc;
5620
5621 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5622 "Entered %s.\n", __func__);
5623
5624 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5625 /* Copy all bits to preserve original setting */
5626 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5627 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5628 mcp->in_mb = MBX_0;
5629 mcp->tov = MBX_TOV_SECONDS;
5630 mcp->flags = 0;
5631 rval = qla2x00_mailbox_command(vha, mcp);
5632
5633 if (rval != QLA_SUCCESS) {
5634 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5635 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5636 } else
5637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5638 "Done %s.\n", __func__);
5639
5640 return rval;
5641 }
5642
5643
5644 int
qla24xx_set_fcp_prio(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t priority,uint16_t * mb)5645 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5646 uint16_t *mb)
5647 {
5648 int rval;
5649 mbx_cmd_t mc;
5650 mbx_cmd_t *mcp = &mc;
5651 struct qla_hw_data *ha = vha->hw;
5652
5653 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5654 "Entered %s.\n", __func__);
5655
5656 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5657 return QLA_FUNCTION_FAILED;
5658
5659 mcp->mb[0] = MBC_PORT_PARAMS;
5660 mcp->mb[1] = loop_id;
5661 if (ha->flags.fcp_prio_enabled)
5662 mcp->mb[2] = BIT_1;
5663 else
5664 mcp->mb[2] = BIT_2;
5665 mcp->mb[4] = priority & 0xf;
5666 mcp->mb[9] = vha->vp_idx;
5667 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5668 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5669 mcp->tov = MBX_TOV_SECONDS;
5670 mcp->flags = 0;
5671 rval = qla2x00_mailbox_command(vha, mcp);
5672 if (mb != NULL) {
5673 mb[0] = mcp->mb[0];
5674 mb[1] = mcp->mb[1];
5675 mb[3] = mcp->mb[3];
5676 mb[4] = mcp->mb[4];
5677 }
5678
5679 if (rval != QLA_SUCCESS) {
5680 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
5681 } else {
5682 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5683 "Done %s.\n", __func__);
5684 }
5685
5686 return rval;
5687 }
5688
5689 int
qla2x00_get_thermal_temp(scsi_qla_host_t * vha,uint16_t * temp)5690 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
5691 {
5692 int rval = QLA_FUNCTION_FAILED;
5693 struct qla_hw_data *ha = vha->hw;
5694 uint8_t byte;
5695
5696 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5697 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5698 "Thermal not supported by this card.\n");
5699 return rval;
5700 }
5701
5702 if (IS_QLA25XX(ha)) {
5703 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5704 ha->pdev->subsystem_device == 0x0175) {
5705 rval = qla2x00_read_sfp(vha, 0, &byte,
5706 0x98, 0x1, 1, BIT_13|BIT_0);
5707 *temp = byte;
5708 return rval;
5709 }
5710 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5711 ha->pdev->subsystem_device == 0x338e) {
5712 rval = qla2x00_read_sfp(vha, 0, &byte,
5713 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5714 *temp = byte;
5715 return rval;
5716 }
5717 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5718 "Thermal not supported by this card.\n");
5719 return rval;
5720 }
5721
5722 if (IS_QLA82XX(ha)) {
5723 *temp = qla82xx_read_temperature(vha);
5724 rval = QLA_SUCCESS;
5725 return rval;
5726 } else if (IS_QLA8044(ha)) {
5727 *temp = qla8044_read_temperature(vha);
5728 rval = QLA_SUCCESS;
5729 return rval;
5730 }
5731
5732 rval = qla2x00_read_asic_temperature(vha, temp);
5733 return rval;
5734 }
5735
5736 int
qla82xx_mbx_intr_enable(scsi_qla_host_t * vha)5737 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5738 {
5739 int rval;
5740 struct qla_hw_data *ha = vha->hw;
5741 mbx_cmd_t mc;
5742 mbx_cmd_t *mcp = &mc;
5743
5744 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5745 "Entered %s.\n", __func__);
5746
5747 if (!IS_FWI2_CAPABLE(ha))
5748 return QLA_FUNCTION_FAILED;
5749
5750 memset(mcp, 0, sizeof(mbx_cmd_t));
5751 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
5752 mcp->mb[1] = 1;
5753
5754 mcp->out_mb = MBX_1|MBX_0;
5755 mcp->in_mb = MBX_0;
5756 mcp->tov = MBX_TOV_SECONDS;
5757 mcp->flags = 0;
5758
5759 rval = qla2x00_mailbox_command(vha, mcp);
5760 if (rval != QLA_SUCCESS) {
5761 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5762 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5763 } else {
5764 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5765 "Done %s.\n", __func__);
5766 }
5767
5768 return rval;
5769 }
5770
5771 int
qla82xx_mbx_intr_disable(scsi_qla_host_t * vha)5772 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5773 {
5774 int rval;
5775 struct qla_hw_data *ha = vha->hw;
5776 mbx_cmd_t mc;
5777 mbx_cmd_t *mcp = &mc;
5778
5779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5780 "Entered %s.\n", __func__);
5781
5782 if (!IS_P3P_TYPE(ha))
5783 return QLA_FUNCTION_FAILED;
5784
5785 memset(mcp, 0, sizeof(mbx_cmd_t));
5786 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
5787 mcp->mb[1] = 0;
5788
5789 mcp->out_mb = MBX_1|MBX_0;
5790 mcp->in_mb = MBX_0;
5791 mcp->tov = MBX_TOV_SECONDS;
5792 mcp->flags = 0;
5793
5794 rval = qla2x00_mailbox_command(vha, mcp);
5795 if (rval != QLA_SUCCESS) {
5796 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5797 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5798 } else {
5799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5800 "Done %s.\n", __func__);
5801 }
5802
5803 return rval;
5804 }
5805
5806 int
qla82xx_md_get_template_size(scsi_qla_host_t * vha)5807 qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5808 {
5809 struct qla_hw_data *ha = vha->hw;
5810 mbx_cmd_t mc;
5811 mbx_cmd_t *mcp = &mc;
5812 int rval = QLA_FUNCTION_FAILED;
5813
5814 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5815 "Entered %s.\n", __func__);
5816
5817 memset(mcp->mb, 0 , sizeof(mcp->mb));
5818 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5819 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5820 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5821 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5822
5823 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5824 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5825 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5826
5827 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5828 mcp->tov = MBX_TOV_SECONDS;
5829 rval = qla2x00_mailbox_command(vha, mcp);
5830
5831 /* Always copy back return mailbox values. */
5832 if (rval != QLA_SUCCESS) {
5833 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5834 "mailbox command FAILED=0x%x, subcode=%x.\n",
5835 (mcp->mb[1] << 16) | mcp->mb[0],
5836 (mcp->mb[3] << 16) | mcp->mb[2]);
5837 } else {
5838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5839 "Done %s.\n", __func__);
5840 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5841 if (!ha->md_template_size) {
5842 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5843 "Null template size obtained.\n");
5844 rval = QLA_FUNCTION_FAILED;
5845 }
5846 }
5847 return rval;
5848 }
5849
5850 int
qla82xx_md_get_template(scsi_qla_host_t * vha)5851 qla82xx_md_get_template(scsi_qla_host_t *vha)
5852 {
5853 struct qla_hw_data *ha = vha->hw;
5854 mbx_cmd_t mc;
5855 mbx_cmd_t *mcp = &mc;
5856 int rval = QLA_FUNCTION_FAILED;
5857
5858 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5859 "Entered %s.\n", __func__);
5860
5861 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5862 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5863 if (!ha->md_tmplt_hdr) {
5864 ql_log(ql_log_warn, vha, 0x1124,
5865 "Unable to allocate memory for Minidump template.\n");
5866 return rval;
5867 }
5868
5869 memset(mcp->mb, 0 , sizeof(mcp->mb));
5870 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5871 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5872 mcp->mb[2] = LSW(RQST_TMPLT);
5873 mcp->mb[3] = MSW(RQST_TMPLT);
5874 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5875 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5876 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5877 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5878 mcp->mb[8] = LSW(ha->md_template_size);
5879 mcp->mb[9] = MSW(ha->md_template_size);
5880
5881 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5882 mcp->tov = MBX_TOV_SECONDS;
5883 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5884 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5885 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5886 rval = qla2x00_mailbox_command(vha, mcp);
5887
5888 if (rval != QLA_SUCCESS) {
5889 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5890 "mailbox command FAILED=0x%x, subcode=%x.\n",
5891 ((mcp->mb[1] << 16) | mcp->mb[0]),
5892 ((mcp->mb[3] << 16) | mcp->mb[2]));
5893 } else
5894 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5895 "Done %s.\n", __func__);
5896 return rval;
5897 }
5898
5899 int
qla8044_md_get_template(scsi_qla_host_t * vha)5900 qla8044_md_get_template(scsi_qla_host_t *vha)
5901 {
5902 struct qla_hw_data *ha = vha->hw;
5903 mbx_cmd_t mc;
5904 mbx_cmd_t *mcp = &mc;
5905 int rval = QLA_FUNCTION_FAILED;
5906 int offset = 0, size = MINIDUMP_SIZE_36K;
5907
5908 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5909 "Entered %s.\n", __func__);
5910
5911 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5912 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5913 if (!ha->md_tmplt_hdr) {
5914 ql_log(ql_log_warn, vha, 0xb11b,
5915 "Unable to allocate memory for Minidump template.\n");
5916 return rval;
5917 }
5918
5919 memset(mcp->mb, 0 , sizeof(mcp->mb));
5920 while (offset < ha->md_template_size) {
5921 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5922 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5923 mcp->mb[2] = LSW(RQST_TMPLT);
5924 mcp->mb[3] = MSW(RQST_TMPLT);
5925 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5926 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5927 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5928 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5929 mcp->mb[8] = LSW(size);
5930 mcp->mb[9] = MSW(size);
5931 mcp->mb[10] = offset & 0x0000FFFF;
5932 mcp->mb[11] = offset & 0xFFFF0000;
5933 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5934 mcp->tov = MBX_TOV_SECONDS;
5935 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5936 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5937 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5938 rval = qla2x00_mailbox_command(vha, mcp);
5939
5940 if (rval != QLA_SUCCESS) {
5941 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5942 "mailbox command FAILED=0x%x, subcode=%x.\n",
5943 ((mcp->mb[1] << 16) | mcp->mb[0]),
5944 ((mcp->mb[3] << 16) | mcp->mb[2]));
5945 return rval;
5946 } else
5947 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5948 "Done %s.\n", __func__);
5949 offset = offset + size;
5950 }
5951 return rval;
5952 }
5953
5954 int
qla81xx_set_led_config(scsi_qla_host_t * vha,uint16_t * led_cfg)5955 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5956 {
5957 int rval;
5958 struct qla_hw_data *ha = vha->hw;
5959 mbx_cmd_t mc;
5960 mbx_cmd_t *mcp = &mc;
5961
5962 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5963 return QLA_FUNCTION_FAILED;
5964
5965 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5966 "Entered %s.\n", __func__);
5967
5968 memset(mcp, 0, sizeof(mbx_cmd_t));
5969 mcp->mb[0] = MBC_SET_LED_CONFIG;
5970 mcp->mb[1] = led_cfg[0];
5971 mcp->mb[2] = led_cfg[1];
5972 if (IS_QLA8031(ha)) {
5973 mcp->mb[3] = led_cfg[2];
5974 mcp->mb[4] = led_cfg[3];
5975 mcp->mb[5] = led_cfg[4];
5976 mcp->mb[6] = led_cfg[5];
5977 }
5978
5979 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5980 if (IS_QLA8031(ha))
5981 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5982 mcp->in_mb = MBX_0;
5983 mcp->tov = MBX_TOV_SECONDS;
5984 mcp->flags = 0;
5985
5986 rval = qla2x00_mailbox_command(vha, mcp);
5987 if (rval != QLA_SUCCESS) {
5988 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5989 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5990 } else {
5991 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5992 "Done %s.\n", __func__);
5993 }
5994
5995 return rval;
5996 }
5997
5998 int
qla81xx_get_led_config(scsi_qla_host_t * vha,uint16_t * led_cfg)5999 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
6000 {
6001 int rval;
6002 struct qla_hw_data *ha = vha->hw;
6003 mbx_cmd_t mc;
6004 mbx_cmd_t *mcp = &mc;
6005
6006 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
6007 return QLA_FUNCTION_FAILED;
6008
6009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
6010 "Entered %s.\n", __func__);
6011
6012 memset(mcp, 0, sizeof(mbx_cmd_t));
6013 mcp->mb[0] = MBC_GET_LED_CONFIG;
6014
6015 mcp->out_mb = MBX_0;
6016 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6017 if (IS_QLA8031(ha))
6018 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
6019 mcp->tov = MBX_TOV_SECONDS;
6020 mcp->flags = 0;
6021
6022 rval = qla2x00_mailbox_command(vha, mcp);
6023 if (rval != QLA_SUCCESS) {
6024 ql_dbg(ql_dbg_mbx, vha, 0x1137,
6025 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6026 } else {
6027 led_cfg[0] = mcp->mb[1];
6028 led_cfg[1] = mcp->mb[2];
6029 if (IS_QLA8031(ha)) {
6030 led_cfg[2] = mcp->mb[3];
6031 led_cfg[3] = mcp->mb[4];
6032 led_cfg[4] = mcp->mb[5];
6033 led_cfg[5] = mcp->mb[6];
6034 }
6035 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
6036 "Done %s.\n", __func__);
6037 }
6038
6039 return rval;
6040 }
6041
6042 int
qla82xx_mbx_beacon_ctl(scsi_qla_host_t * vha,int enable)6043 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
6044 {
6045 int rval;
6046 struct qla_hw_data *ha = vha->hw;
6047 mbx_cmd_t mc;
6048 mbx_cmd_t *mcp = &mc;
6049
6050 if (!IS_P3P_TYPE(ha))
6051 return QLA_FUNCTION_FAILED;
6052
6053 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
6054 "Entered %s.\n", __func__);
6055
6056 memset(mcp, 0, sizeof(mbx_cmd_t));
6057 mcp->mb[0] = MBC_SET_LED_CONFIG;
6058 if (enable)
6059 mcp->mb[7] = 0xE;
6060 else
6061 mcp->mb[7] = 0xD;
6062
6063 mcp->out_mb = MBX_7|MBX_0;
6064 mcp->in_mb = MBX_0;
6065 mcp->tov = MBX_TOV_SECONDS;
6066 mcp->flags = 0;
6067
6068 rval = qla2x00_mailbox_command(vha, mcp);
6069 if (rval != QLA_SUCCESS) {
6070 ql_dbg(ql_dbg_mbx, vha, 0x1128,
6071 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6072 } else {
6073 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
6074 "Done %s.\n", __func__);
6075 }
6076
6077 return rval;
6078 }
6079
6080 int
qla83xx_wr_reg(scsi_qla_host_t * vha,uint32_t reg,uint32_t data)6081 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6082 {
6083 int rval;
6084 struct qla_hw_data *ha = vha->hw;
6085 mbx_cmd_t mc;
6086 mbx_cmd_t *mcp = &mc;
6087
6088 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6089 return QLA_FUNCTION_FAILED;
6090
6091 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
6092 "Entered %s.\n", __func__);
6093
6094 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
6095 mcp->mb[1] = LSW(reg);
6096 mcp->mb[2] = MSW(reg);
6097 mcp->mb[3] = LSW(data);
6098 mcp->mb[4] = MSW(data);
6099 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6100
6101 mcp->in_mb = MBX_1|MBX_0;
6102 mcp->tov = MBX_TOV_SECONDS;
6103 mcp->flags = 0;
6104 rval = qla2x00_mailbox_command(vha, mcp);
6105
6106 if (rval != QLA_SUCCESS) {
6107 ql_dbg(ql_dbg_mbx, vha, 0x1131,
6108 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6109 } else {
6110 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6111 "Done %s.\n", __func__);
6112 }
6113
6114 return rval;
6115 }
6116
6117 int
qla2x00_port_logout(scsi_qla_host_t * vha,struct fc_port * fcport)6118 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
6119 {
6120 int rval;
6121 struct qla_hw_data *ha = vha->hw;
6122 mbx_cmd_t mc;
6123 mbx_cmd_t *mcp = &mc;
6124
6125 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
6126 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
6127 "Implicit LOGO Unsupported.\n");
6128 return QLA_FUNCTION_FAILED;
6129 }
6130
6131
6132 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
6133 "Entering %s.\n", __func__);
6134
6135 /* Perform Implicit LOGO. */
6136 mcp->mb[0] = MBC_PORT_LOGOUT;
6137 mcp->mb[1] = fcport->loop_id;
6138 mcp->mb[10] = BIT_15;
6139 mcp->out_mb = MBX_10|MBX_1|MBX_0;
6140 mcp->in_mb = MBX_0;
6141 mcp->tov = MBX_TOV_SECONDS;
6142 mcp->flags = 0;
6143 rval = qla2x00_mailbox_command(vha, mcp);
6144 if (rval != QLA_SUCCESS)
6145 ql_dbg(ql_dbg_mbx, vha, 0x113d,
6146 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6147 else
6148 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
6149 "Done %s.\n", __func__);
6150
6151 return rval;
6152 }
6153
6154 int
qla83xx_rd_reg(scsi_qla_host_t * vha,uint32_t reg,uint32_t * data)6155 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
6156 {
6157 int rval;
6158 mbx_cmd_t mc;
6159 mbx_cmd_t *mcp = &mc;
6160 struct qla_hw_data *ha = vha->hw;
6161 unsigned long retry_max_time = jiffies + (2 * HZ);
6162
6163 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6164 return QLA_FUNCTION_FAILED;
6165
6166 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
6167
6168 retry_rd_reg:
6169 mcp->mb[0] = MBC_READ_REMOTE_REG;
6170 mcp->mb[1] = LSW(reg);
6171 mcp->mb[2] = MSW(reg);
6172 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6173 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
6174 mcp->tov = MBX_TOV_SECONDS;
6175 mcp->flags = 0;
6176 rval = qla2x00_mailbox_command(vha, mcp);
6177
6178 if (rval != QLA_SUCCESS) {
6179 ql_dbg(ql_dbg_mbx, vha, 0x114c,
6180 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6181 rval, mcp->mb[0], mcp->mb[1]);
6182 } else {
6183 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
6184 if (*data == QLA8XXX_BAD_VALUE) {
6185 /*
6186 * During soft-reset CAMRAM register reads might
6187 * return 0xbad0bad0. So retry for MAX of 2 sec
6188 * while reading camram registers.
6189 */
6190 if (time_after(jiffies, retry_max_time)) {
6191 ql_dbg(ql_dbg_mbx, vha, 0x1141,
6192 "Failure to read CAMRAM register. "
6193 "data=0x%x.\n", *data);
6194 return QLA_FUNCTION_FAILED;
6195 }
6196 msleep(100);
6197 goto retry_rd_reg;
6198 }
6199 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
6200 }
6201
6202 return rval;
6203 }
6204
6205 int
qla83xx_restart_nic_firmware(scsi_qla_host_t * vha)6206 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
6207 {
6208 int rval;
6209 mbx_cmd_t mc;
6210 mbx_cmd_t *mcp = &mc;
6211 struct qla_hw_data *ha = vha->hw;
6212
6213 if (!IS_QLA83XX(ha))
6214 return QLA_FUNCTION_FAILED;
6215
6216 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
6217
6218 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
6219 mcp->out_mb = MBX_0;
6220 mcp->in_mb = MBX_1|MBX_0;
6221 mcp->tov = MBX_TOV_SECONDS;
6222 mcp->flags = 0;
6223 rval = qla2x00_mailbox_command(vha, mcp);
6224
6225 if (rval != QLA_SUCCESS) {
6226 ql_dbg(ql_dbg_mbx, vha, 0x1144,
6227 "Failed=%x mb[0]=%x mb[1]=%x.\n",
6228 rval, mcp->mb[0], mcp->mb[1]);
6229 qla2xxx_dump_fw(vha);
6230 } else {
6231 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
6232 }
6233
6234 return rval;
6235 }
6236
6237 int
qla83xx_access_control(scsi_qla_host_t * vha,uint16_t options,uint32_t start_addr,uint32_t end_addr,uint16_t * sector_size)6238 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
6239 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
6240 {
6241 int rval;
6242 mbx_cmd_t mc;
6243 mbx_cmd_t *mcp = &mc;
6244 uint8_t subcode = (uint8_t)options;
6245 struct qla_hw_data *ha = vha->hw;
6246
6247 if (!IS_QLA8031(ha))
6248 return QLA_FUNCTION_FAILED;
6249
6250 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
6251
6252 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
6253 mcp->mb[1] = options;
6254 mcp->out_mb = MBX_1|MBX_0;
6255 if (subcode & BIT_2) {
6256 mcp->mb[2] = LSW(start_addr);
6257 mcp->mb[3] = MSW(start_addr);
6258 mcp->mb[4] = LSW(end_addr);
6259 mcp->mb[5] = MSW(end_addr);
6260 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
6261 }
6262 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6263 if (!(subcode & (BIT_2 | BIT_5)))
6264 mcp->in_mb |= MBX_4|MBX_3;
6265 mcp->tov = MBX_TOV_SECONDS;
6266 mcp->flags = 0;
6267 rval = qla2x00_mailbox_command(vha, mcp);
6268
6269 if (rval != QLA_SUCCESS) {
6270 ql_dbg(ql_dbg_mbx, vha, 0x1147,
6271 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
6272 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
6273 mcp->mb[4]);
6274 qla2xxx_dump_fw(vha);
6275 } else {
6276 if (subcode & BIT_5)
6277 *sector_size = mcp->mb[1];
6278 else if (subcode & (BIT_6 | BIT_7)) {
6279 ql_dbg(ql_dbg_mbx, vha, 0x1148,
6280 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6281 } else if (subcode & (BIT_3 | BIT_4)) {
6282 ql_dbg(ql_dbg_mbx, vha, 0x1149,
6283 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
6284 }
6285 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
6286 }
6287
6288 return rval;
6289 }
6290
6291 int
qla2x00_dump_mctp_data(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t addr,uint32_t size)6292 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
6293 uint32_t size)
6294 {
6295 int rval;
6296 mbx_cmd_t mc;
6297 mbx_cmd_t *mcp = &mc;
6298
6299 if (!IS_MCTP_CAPABLE(vha->hw))
6300 return QLA_FUNCTION_FAILED;
6301
6302 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
6303 "Entered %s.\n", __func__);
6304
6305 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
6306 mcp->mb[1] = LSW(addr);
6307 mcp->mb[2] = MSW(req_dma);
6308 mcp->mb[3] = LSW(req_dma);
6309 mcp->mb[4] = MSW(size);
6310 mcp->mb[5] = LSW(size);
6311 mcp->mb[6] = MSW(MSD(req_dma));
6312 mcp->mb[7] = LSW(MSD(req_dma));
6313 mcp->mb[8] = MSW(addr);
6314 /* Setting RAM ID to valid */
6315 /* For MCTP RAM ID is 0x40 */
6316 mcp->mb[10] = BIT_7 | 0x40;
6317
6318 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
6319 MBX_0;
6320
6321 mcp->in_mb = MBX_0;
6322 mcp->tov = MBX_TOV_SECONDS;
6323 mcp->flags = 0;
6324 rval = qla2x00_mailbox_command(vha, mcp);
6325
6326 if (rval != QLA_SUCCESS) {
6327 ql_dbg(ql_dbg_mbx, vha, 0x114e,
6328 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6329 } else {
6330 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
6331 "Done %s.\n", __func__);
6332 }
6333
6334 return rval;
6335 }
6336
6337 int
qla26xx_dport_diagnostics(scsi_qla_host_t * vha,void * dd_buf,uint size,uint options)6338 qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
6339 void *dd_buf, uint size, uint options)
6340 {
6341 int rval;
6342 mbx_cmd_t mc;
6343 mbx_cmd_t *mcp = &mc;
6344 dma_addr_t dd_dma;
6345
6346 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
6347 !IS_QLA28XX(vha->hw))
6348 return QLA_FUNCTION_FAILED;
6349
6350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
6351 "Entered %s.\n", __func__);
6352
6353 dd_dma = dma_map_single(&vha->hw->pdev->dev,
6354 dd_buf, size, DMA_FROM_DEVICE);
6355 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) {
6356 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
6357 return QLA_MEMORY_ALLOC_FAILED;
6358 }
6359
6360 memset(dd_buf, 0, size);
6361
6362 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
6363 mcp->mb[1] = options;
6364 mcp->mb[2] = MSW(LSD(dd_dma));
6365 mcp->mb[3] = LSW(LSD(dd_dma));
6366 mcp->mb[6] = MSW(MSD(dd_dma));
6367 mcp->mb[7] = LSW(MSD(dd_dma));
6368 mcp->mb[8] = size;
6369 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6370 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
6371 mcp->buf_size = size;
6372 mcp->flags = MBX_DMA_IN;
6373 mcp->tov = MBX_TOV_SECONDS * 4;
6374 rval = qla2x00_mailbox_command(vha, mcp);
6375
6376 if (rval != QLA_SUCCESS) {
6377 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
6378 } else {
6379 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
6380 "Done %s.\n", __func__);
6381 }
6382
6383 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
6384 size, DMA_FROM_DEVICE);
6385
6386 return rval;
6387 }
6388
qla2x00_async_mb_sp_done(srb_t * sp,int res)6389 static void qla2x00_async_mb_sp_done(srb_t *sp, int res)
6390 {
6391 sp->u.iocb_cmd.u.mbx.rc = res;
6392
6393 complete(&sp->u.iocb_cmd.u.mbx.comp);
6394 /* don't free sp here. Let the caller do the free */
6395 }
6396
6397 /*
6398 * This mailbox uses the iocb interface to send MB command.
6399 * This allows non-critial (non chip setup) command to go
6400 * out in parrallel.
6401 */
qla24xx_send_mb_cmd(struct scsi_qla_host * vha,mbx_cmd_t * mcp)6402 int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
6403 {
6404 int rval = QLA_FUNCTION_FAILED;
6405 srb_t *sp;
6406 struct srb_iocb *c;
6407
6408 if (!vha->hw->flags.fw_started)
6409 goto done;
6410
6411 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
6412 if (!sp)
6413 goto done;
6414
6415 sp->type = SRB_MB_IOCB;
6416 sp->name = mb_to_str(mcp->mb[0]);
6417
6418 c = &sp->u.iocb_cmd;
6419 c->timeout = qla2x00_async_iocb_timeout;
6420 init_completion(&c->u.mbx.comp);
6421
6422 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
6423
6424 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
6425
6426 sp->done = qla2x00_async_mb_sp_done;
6427
6428 rval = qla2x00_start_sp(sp);
6429 if (rval != QLA_SUCCESS) {
6430 ql_dbg(ql_dbg_mbx, vha, 0x1018,
6431 "%s: %s Failed submission. %x.\n",
6432 __func__, sp->name, rval);
6433 goto done_free_sp;
6434 }
6435
6436 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
6437 sp->name, sp->handle);
6438
6439 wait_for_completion(&c->u.mbx.comp);
6440 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
6441
6442 rval = c->u.mbx.rc;
6443 switch (rval) {
6444 case QLA_FUNCTION_TIMEOUT:
6445 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
6446 __func__, sp->name, rval);
6447 break;
6448 case QLA_SUCCESS:
6449 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
6450 __func__, sp->name);
6451 break;
6452 default:
6453 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
6454 __func__, sp->name, rval);
6455 break;
6456 }
6457
6458 done_free_sp:
6459 sp->free(sp);
6460 done:
6461 return rval;
6462 }
6463
6464 /*
6465 * qla24xx_gpdb_wait
6466 * NOTE: Do not call this routine from DPC thread
6467 */
qla24xx_gpdb_wait(struct scsi_qla_host * vha,fc_port_t * fcport,u8 opt)6468 int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
6469 {
6470 int rval = QLA_FUNCTION_FAILED;
6471 dma_addr_t pd_dma;
6472 struct port_database_24xx *pd;
6473 struct qla_hw_data *ha = vha->hw;
6474 mbx_cmd_t mc;
6475
6476 if (!vha->hw->flags.fw_started)
6477 goto done;
6478
6479 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
6480 if (pd == NULL) {
6481 ql_log(ql_log_warn, vha, 0xd047,
6482 "Failed to allocate port database structure.\n");
6483 goto done_free_sp;
6484 }
6485
6486 memset(&mc, 0, sizeof(mc));
6487 mc.mb[0] = MBC_GET_PORT_DATABASE;
6488 mc.mb[1] = fcport->loop_id;
6489 mc.mb[2] = MSW(pd_dma);
6490 mc.mb[3] = LSW(pd_dma);
6491 mc.mb[6] = MSW(MSD(pd_dma));
6492 mc.mb[7] = LSW(MSD(pd_dma));
6493 mc.mb[9] = vha->vp_idx;
6494 mc.mb[10] = opt;
6495
6496 rval = qla24xx_send_mb_cmd(vha, &mc);
6497 if (rval != QLA_SUCCESS) {
6498 ql_dbg(ql_dbg_mbx, vha, 0x1193,
6499 "%s: %8phC fail\n", __func__, fcport->port_name);
6500 goto done_free_sp;
6501 }
6502
6503 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
6504
6505 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
6506 __func__, fcport->port_name);
6507
6508 done_free_sp:
6509 if (pd)
6510 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
6511 done:
6512 return rval;
6513 }
6514
__qla24xx_parse_gpdb(struct scsi_qla_host * vha,fc_port_t * fcport,struct port_database_24xx * pd)6515 int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
6516 struct port_database_24xx *pd)
6517 {
6518 int rval = QLA_SUCCESS;
6519 uint64_t zero = 0;
6520 u8 current_login_state, last_login_state;
6521
6522 if (NVME_TARGET(vha->hw, fcport)) {
6523 current_login_state = pd->current_login_state >> 4;
6524 last_login_state = pd->last_login_state >> 4;
6525 } else {
6526 current_login_state = pd->current_login_state & 0xf;
6527 last_login_state = pd->last_login_state & 0xf;
6528 }
6529
6530 /* Check for logged in state. */
6531 if (current_login_state != PDS_PRLI_COMPLETE) {
6532 ql_dbg(ql_dbg_mbx, vha, 0x119a,
6533 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
6534 current_login_state, last_login_state, fcport->loop_id);
6535 rval = QLA_FUNCTION_FAILED;
6536 goto gpd_error_out;
6537 }
6538
6539 if (fcport->loop_id == FC_NO_LOOP_ID ||
6540 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
6541 memcmp(fcport->port_name, pd->port_name, 8))) {
6542 /* We lost the device mid way. */
6543 rval = QLA_NOT_LOGGED_IN;
6544 goto gpd_error_out;
6545 }
6546
6547 /* Names are little-endian. */
6548 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
6549 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
6550
6551 /* Get port_id of device. */
6552 fcport->d_id.b.domain = pd->port_id[0];
6553 fcport->d_id.b.area = pd->port_id[1];
6554 fcport->d_id.b.al_pa = pd->port_id[2];
6555 fcport->d_id.b.rsvd_1 = 0;
6556
6557 if (NVME_TARGET(vha->hw, fcport)) {
6558 fcport->port_type = FCT_NVME;
6559 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0)
6560 fcport->port_type |= FCT_NVME_INITIATOR;
6561 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6562 fcport->port_type |= FCT_NVME_TARGET;
6563 if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
6564 fcport->port_type |= FCT_NVME_DISCOVERY;
6565 } else {
6566 /* If not target must be initiator or unknown type. */
6567 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6568 fcport->port_type = FCT_INITIATOR;
6569 else
6570 fcport->port_type = FCT_TARGET;
6571 }
6572 /* Passback COS information. */
6573 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6574 FC_COS_CLASS2 : FC_COS_CLASS3;
6575
6576 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6577 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6578 fcport->conf_compl_supported = 1;
6579 }
6580
6581 gpd_error_out:
6582 return rval;
6583 }
6584
6585 /*
6586 * qla24xx_gidlist__wait
6587 * NOTE: don't call this routine from DPC thread.
6588 */
qla24xx_gidlist_wait(struct scsi_qla_host * vha,void * id_list,dma_addr_t id_list_dma,uint16_t * entries)6589 int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6590 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6591 {
6592 int rval = QLA_FUNCTION_FAILED;
6593 mbx_cmd_t mc;
6594
6595 if (!vha->hw->flags.fw_started)
6596 goto done;
6597
6598 memset(&mc, 0, sizeof(mc));
6599 mc.mb[0] = MBC_GET_ID_LIST;
6600 mc.mb[2] = MSW(id_list_dma);
6601 mc.mb[3] = LSW(id_list_dma);
6602 mc.mb[6] = MSW(MSD(id_list_dma));
6603 mc.mb[7] = LSW(MSD(id_list_dma));
6604 mc.mb[8] = 0;
6605 mc.mb[9] = vha->vp_idx;
6606
6607 rval = qla24xx_send_mb_cmd(vha, &mc);
6608 if (rval != QLA_SUCCESS) {
6609 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6610 "%s: fail\n", __func__);
6611 } else {
6612 *entries = mc.mb[1];
6613 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6614 "%s: done\n", __func__);
6615 }
6616 done:
6617 return rval;
6618 }
6619
qla27xx_set_zio_threshold(scsi_qla_host_t * vha,uint16_t value)6620 int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
6621 {
6622 int rval;
6623 mbx_cmd_t mc;
6624 mbx_cmd_t *mcp = &mc;
6625
6626 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
6627 "Entered %s\n", __func__);
6628
6629 memset(mcp->mb, 0 , sizeof(mcp->mb));
6630 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6631 mcp->mb[1] = 1;
6632 mcp->mb[2] = value;
6633 mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
6634 mcp->in_mb = MBX_2 | MBX_0;
6635 mcp->tov = MBX_TOV_SECONDS;
6636 mcp->flags = 0;
6637
6638 rval = qla2x00_mailbox_command(vha, mcp);
6639
6640 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
6641 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6642
6643 return rval;
6644 }
6645
qla27xx_get_zio_threshold(scsi_qla_host_t * vha,uint16_t * value)6646 int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
6647 {
6648 int rval;
6649 mbx_cmd_t mc;
6650 mbx_cmd_t *mcp = &mc;
6651
6652 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
6653 "Entered %s\n", __func__);
6654
6655 memset(mcp->mb, 0, sizeof(mcp->mb));
6656 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6657 mcp->mb[1] = 0;
6658 mcp->out_mb = MBX_1 | MBX_0;
6659 mcp->in_mb = MBX_2 | MBX_0;
6660 mcp->tov = MBX_TOV_SECONDS;
6661 mcp->flags = 0;
6662
6663 rval = qla2x00_mailbox_command(vha, mcp);
6664 if (rval == QLA_SUCCESS)
6665 *value = mc.mb[2];
6666
6667 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
6668 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6669
6670 return rval;
6671 }
6672
6673 int
qla2x00_read_sfp_dev(struct scsi_qla_host * vha,char * buf,int count)6674 qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count)
6675 {
6676 struct qla_hw_data *ha = vha->hw;
6677 uint16_t iter, addr, offset;
6678 dma_addr_t phys_addr;
6679 int rval, c;
6680 u8 *sfp_data;
6681
6682 memset(ha->sfp_data, 0, SFP_DEV_SIZE);
6683 addr = 0xa0;
6684 phys_addr = ha->sfp_data_dma;
6685 sfp_data = ha->sfp_data;
6686 offset = c = 0;
6687
6688 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) {
6689 if (iter == 4) {
6690 /* Skip to next device address. */
6691 addr = 0xa2;
6692 offset = 0;
6693 }
6694
6695 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data,
6696 addr, offset, SFP_BLOCK_SIZE, BIT_1);
6697 if (rval != QLA_SUCCESS) {
6698 ql_log(ql_log_warn, vha, 0x706d,
6699 "Unable to read SFP data (%x/%x/%x).\n", rval,
6700 addr, offset);
6701
6702 return rval;
6703 }
6704
6705 if (buf && (c < count)) {
6706 u16 sz;
6707
6708 if ((count - c) >= SFP_BLOCK_SIZE)
6709 sz = SFP_BLOCK_SIZE;
6710 else
6711 sz = count - c;
6712
6713 memcpy(buf, sfp_data, sz);
6714 buf += SFP_BLOCK_SIZE;
6715 c += sz;
6716 }
6717 phys_addr += SFP_BLOCK_SIZE;
6718 sfp_data += SFP_BLOCK_SIZE;
6719 offset += SFP_BLOCK_SIZE;
6720 }
6721
6722 return rval;
6723 }
6724
qla24xx_res_count_wait(struct scsi_qla_host * vha,uint16_t * out_mb,int out_mb_sz)6725 int qla24xx_res_count_wait(struct scsi_qla_host *vha,
6726 uint16_t *out_mb, int out_mb_sz)
6727 {
6728 int rval = QLA_FUNCTION_FAILED;
6729 mbx_cmd_t mc;
6730
6731 if (!vha->hw->flags.fw_started)
6732 goto done;
6733
6734 memset(&mc, 0, sizeof(mc));
6735 mc.mb[0] = MBC_GET_RESOURCE_COUNTS;
6736
6737 rval = qla24xx_send_mb_cmd(vha, &mc);
6738 if (rval != QLA_SUCCESS) {
6739 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6740 "%s: fail\n", __func__);
6741 } else {
6742 if (out_mb_sz <= SIZEOF_IOCB_MB_REG)
6743 memcpy(out_mb, mc.mb, out_mb_sz);
6744 else
6745 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG);
6746
6747 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6748 "%s: done\n", __func__);
6749 }
6750 done:
6751 return rval;
6752 }
6753
qla28xx_secure_flash_update(scsi_qla_host_t * vha,uint16_t opts,uint16_t region,uint32_t len,dma_addr_t sfub_dma_addr,uint32_t sfub_len)6754 int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
6755 uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
6756 uint32_t sfub_len)
6757 {
6758 int rval;
6759 mbx_cmd_t mc;
6760 mbx_cmd_t *mcp = &mc;
6761
6762 mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
6763 mcp->mb[1] = opts;
6764 mcp->mb[2] = region;
6765 mcp->mb[3] = MSW(len);
6766 mcp->mb[4] = LSW(len);
6767 mcp->mb[5] = MSW(sfub_dma_addr);
6768 mcp->mb[6] = LSW(sfub_dma_addr);
6769 mcp->mb[7] = MSW(MSD(sfub_dma_addr));
6770 mcp->mb[8] = LSW(MSD(sfub_dma_addr));
6771 mcp->mb[9] = sfub_len;
6772 mcp->out_mb =
6773 MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6774 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6775 mcp->tov = MBX_TOV_SECONDS;
6776 mcp->flags = 0;
6777 rval = qla2x00_mailbox_command(vha, mcp);
6778
6779 if (rval != QLA_SUCCESS) {
6780 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
6781 __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
6782 mcp->mb[2]);
6783 }
6784
6785 return rval;
6786 }
6787
qla2xxx_write_remote_register(scsi_qla_host_t * vha,uint32_t addr,uint32_t data)6788 int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6789 uint32_t data)
6790 {
6791 int rval;
6792 mbx_cmd_t mc;
6793 mbx_cmd_t *mcp = &mc;
6794
6795 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6796 "Entered %s.\n", __func__);
6797
6798 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
6799 mcp->mb[1] = LSW(addr);
6800 mcp->mb[2] = MSW(addr);
6801 mcp->mb[3] = LSW(data);
6802 mcp->mb[4] = MSW(data);
6803 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6804 mcp->in_mb = MBX_1|MBX_0;
6805 mcp->tov = MBX_TOV_SECONDS;
6806 mcp->flags = 0;
6807 rval = qla2x00_mailbox_command(vha, mcp);
6808
6809 if (rval != QLA_SUCCESS) {
6810 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6811 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6812 } else {
6813 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6814 "Done %s.\n", __func__);
6815 }
6816
6817 return rval;
6818 }
6819
qla2xxx_read_remote_register(scsi_qla_host_t * vha,uint32_t addr,uint32_t * data)6820 int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
6821 uint32_t *data)
6822 {
6823 int rval;
6824 mbx_cmd_t mc;
6825 mbx_cmd_t *mcp = &mc;
6826
6827 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
6828 "Entered %s.\n", __func__);
6829
6830 mcp->mb[0] = MBC_READ_REMOTE_REG;
6831 mcp->mb[1] = LSW(addr);
6832 mcp->mb[2] = MSW(addr);
6833 mcp->out_mb = MBX_2|MBX_1|MBX_0;
6834 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6835 mcp->tov = MBX_TOV_SECONDS;
6836 mcp->flags = 0;
6837 rval = qla2x00_mailbox_command(vha, mcp);
6838
6839 *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]);
6840
6841 if (rval != QLA_SUCCESS) {
6842 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
6843 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6844 } else {
6845 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
6846 "Done %s.\n", __func__);
6847 }
6848
6849 return rval;
6850 }
6851
6852 int
ql26xx_led_config(scsi_qla_host_t * vha,uint16_t options,uint16_t * led)6853 ql26xx_led_config(scsi_qla_host_t *vha, uint16_t options, uint16_t *led)
6854 {
6855 struct qla_hw_data *ha = vha->hw;
6856 mbx_cmd_t mc;
6857 mbx_cmd_t *mcp = &mc;
6858 int rval;
6859
6860 if (!IS_QLA2031(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
6861 return QLA_FUNCTION_FAILED;
6862
6863 ql_dbg(ql_dbg_mbx, vha, 0x7070, "Entered %s (options=%x).\n",
6864 __func__, options);
6865
6866 mcp->mb[0] = MBC_SET_GET_FC_LED_CONFIG;
6867 mcp->mb[1] = options;
6868 mcp->out_mb = MBX_1|MBX_0;
6869 mcp->in_mb = MBX_1|MBX_0;
6870 if (options & BIT_0) {
6871 if (options & BIT_1) {
6872 mcp->mb[2] = led[2];
6873 mcp->out_mb |= MBX_2;
6874 }
6875 if (options & BIT_2) {
6876 mcp->mb[3] = led[0];
6877 mcp->out_mb |= MBX_3;
6878 }
6879 if (options & BIT_3) {
6880 mcp->mb[4] = led[1];
6881 mcp->out_mb |= MBX_4;
6882 }
6883 } else {
6884 mcp->in_mb |= MBX_4|MBX_3|MBX_2;
6885 }
6886 mcp->tov = MBX_TOV_SECONDS;
6887 mcp->flags = 0;
6888 rval = qla2x00_mailbox_command(vha, mcp);
6889 if (rval) {
6890 ql_dbg(ql_dbg_mbx, vha, 0x7071, "Failed %s %x (mb=%x,%x)\n",
6891 __func__, rval, mcp->mb[0], mcp->mb[1]);
6892 return rval;
6893 }
6894
6895 if (options & BIT_0) {
6896 ha->beacon_blink_led = 0;
6897 ql_dbg(ql_dbg_mbx, vha, 0x7072, "Done %s\n", __func__);
6898 } else {
6899 led[2] = mcp->mb[2];
6900 led[0] = mcp->mb[3];
6901 led[1] = mcp->mb[4];
6902 ql_dbg(ql_dbg_mbx, vha, 0x7073, "Done %s (led=%x,%x,%x)\n",
6903 __func__, led[0], led[1], led[2]);
6904 }
6905
6906 return rval;
6907 }
6908
