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Searched refs:cpg (Results 1 – 25 of 87) sorted by relevance

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/Linux-v5.10/drivers/clk/renesas/
DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
Dclk-sh73a0.c75 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
86 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
91 void __iomem *enable_reg = cpg->reg; in sh73a0_cpg_register_clock()
111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
120 void __iomem *dsi_reg = cpg->reg + in sh73a0_cpg_register_clock()
157 cpg->reg + reg, shift, width, 0, in sh73a0_cpg_register_clock()
158 table, &cpg->lock); in sh73a0_cpg_register_clock()
164 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
175 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in sh73a0_cpg_clocks_init()
177 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
[all …]
/Linux-v5.10/arch/arm64/boot/dts/renesas/
Dhihope-rev4.dtsi95 clocks = <&cpg CPG_MOD 1005>,
96 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
97 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
98 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
99 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
100 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
101 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
102 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
103 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
104 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
93 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
105 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
174 clocks = <&cpg CPG_MOD 402>;
176 resets = <&cpg 402>;
190 clocks = <&cpg CPG_MOD 912>;
192 resets = <&cpg 912>;
205 clocks = <&cpg CPG_MOD 911>;
207 resets = <&cpg 911>;
220 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
80 clocks = <&cpg CPG_MOD 402>;
82 resets = <&cpg 402>;
96 clocks = <&cpg CPG_MOD 912>;
98 resets = <&cpg 912>;
111 clocks = <&cpg CPG_MOD 911>;
113 resets = <&cpg 911>;
126 clocks = <&cpg CPG_MOD 910>;
128 resets = <&cpg 910>;
141 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
160 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
174 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
188 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
202 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
218 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
231 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
244 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
257 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
367 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a774b1.dtsi10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
85 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
96 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
159 clocks = <&cpg CPG_MOD 402>;
161 resets = <&cpg 402>;
175 clocks = <&cpg CPG_MOD 912>;
177 resets = <&cpg 912>;
190 clocks = <&cpg CPG_MOD 911>;
192 resets = <&cpg 911>;
205 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77960.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
165 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
179 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
195 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
234 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
336 clocks = <&cpg CPG_MOD 402>;
338 resets = <&cpg 402>;
352 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
117 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
129 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
206 clocks = <&cpg CPG_MOD 402>;
208 resets = <&cpg 402>;
222 clocks = <&cpg CPG_MOD 912>;
224 resets = <&cpg 912>;
237 clocks = <&cpg CPG_MOD 911>;
239 resets = <&cpg 911>;
252 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a774e1.dtsi10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
138 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
152 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
166 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
180 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
196 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
209 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
222 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
235 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
340 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a77980.dtsi9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
141 clocks = <&cpg CPG_MOD 402>;
143 resets = <&cpg 402>;
157 clocks = <&cpg CPG_MOD 912>;
159 resets = <&cpg 912>;
172 clocks = <&cpg CPG_MOD 911>;
[all …]
Dr8a77970.dtsi9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
42 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
52 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
111 clocks = <&cpg CPG_MOD 402>;
113 resets = <&cpg 402>;
127 clocks = <&cpg CPG_MOD 912>;
129 resets = <&cpg 912>;
142 clocks = <&cpg CPG_MOD 911>;
144 resets = <&cpg 911>;
157 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a774a1.dtsi10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
141 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
154 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
205 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
285 clocks = <&cpg CPG_MOD 402>;
287 resets = <&cpg 402>;
301 clocks = <&cpg CPG_MOD 912>;
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
163 clocks = <&cpg CPG_MOD 402>;
165 resets = <&cpg 402>;
179 clocks = <&cpg CPG_MOD 912>;
181 resets = <&cpg 912>;
194 clocks = <&cpg CPG_MOD 911>;
196 resets = <&cpg 911>;
209 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
93 clocks = <&cpg CPG_MOD 402>;
95 resets = <&cpg 402>;
109 clocks = <&cpg CPG_MOD 912>;
111 resets = <&cpg 912>;
124 clocks = <&cpg CPG_MOD 911>;
126 resets = <&cpg 911>;
139 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
138 clocks = <&cpg CPG_MOD 912>;
140 resets = <&cpg 912>;
153 clocks = <&cpg CPG_MOD 911>;
155 resets = <&cpg 911>;
168 clocks = <&cpg CPG_MOD 910>;
170 resets = <&cpg 910>;
183 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7742.dtsi8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
57 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
99 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
120 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
141 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
151 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
161 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
171 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
245 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
130 clocks = <&cpg CPG_MOD 402>;
132 resets = <&cpg 402>;
146 clocks = <&cpg CPG_MOD 912>;
148 resets = <&cpg 912>;
161 clocks = <&cpg CPG_MOD 911>;
163 resets = <&cpg 911>;
176 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
142 clocks = <&cpg CPG_MOD 402>;
144 resets = <&cpg 402>;
158 clocks = <&cpg CPG_MOD 912>;
160 resets = <&cpg 912>;
173 clocks = <&cpg CPG_MOD 911>;
175 resets = <&cpg 911>;
188 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
113 clocks = <&cpg CPG_MOD 402>;
115 resets = <&cpg 402>;
129 clocks = <&cpg CPG_MOD 912>;
131 resets = <&cpg 912>;
144 clocks = <&cpg CPG_MOD 911>;
146 resets = <&cpg 911>;
159 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
142 clocks = <&cpg CPG_MOD 402>;
144 resets = <&cpg 402>;
158 clocks = <&cpg CPG_MOD 912>;
160 resets = <&cpg 912>;
173 clocks = <&cpg CPG_MOD 911>;
175 resets = <&cpg 911>;
188 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
121 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
142 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
163 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
174 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
185 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
196 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
270 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr7s9210.dtsi10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
82 clocks = <&cpg CPG_MOD 47>;
84 power-domains = <&cpg>;
99 clocks = <&cpg CPG_MOD 46>;
101 power-domains = <&cpg>;
116 clocks = <&cpg CPG_MOD 45>;
118 power-domains = <&cpg>;
133 clocks = <&cpg CPG_MOD 44>;
135 power-domains = <&cpg>;
150 clocks = <&cpg CPG_MOD 43>;
[all …]

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