Lines Matching refs:cpg
75 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
86 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
91 void __iomem *enable_reg = cpg->reg; in sh73a0_cpg_register_clock()
111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
120 void __iomem *dsi_reg = cpg->reg + in sh73a0_cpg_register_clock()
157 cpg->reg + reg, shift, width, 0, in sh73a0_cpg_register_clock()
158 table, &cpg->lock); in sh73a0_cpg_register_clock()
164 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
175 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in sh73a0_cpg_clocks_init()
177 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
184 spin_lock_init(&cpg->lock); in sh73a0_cpg_clocks_init()
186 cpg->data.clks = clks; in sh73a0_cpg_clocks_init()
187 cpg->data.clk_num = num_clks; in sh73a0_cpg_clocks_init()
189 cpg->reg = of_iomap(np, 0); in sh73a0_cpg_clocks_init()
190 if (WARN_ON(cpg->reg == NULL)) in sh73a0_cpg_clocks_init()
194 writel(0x108, cpg->reg + CPG_SD0CKCR); in sh73a0_cpg_clocks_init()
195 writel(0x108, cpg->reg + CPG_SD1CKCR); in sh73a0_cpg_clocks_init()
196 writel(0x108, cpg->reg + CPG_SD2CKCR); in sh73a0_cpg_clocks_init()
205 clk = sh73a0_cpg_register_clock(np, cpg, name); in sh73a0_cpg_clocks_init()
210 cpg->data.clks[i] = clk; in sh73a0_cpg_clocks_init()
213 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); in sh73a0_cpg_clocks_init()