Searched refs:controller_base (Results 1 – 2 of 2) sorted by relevance
714 void __iomem *controller_base = mt->thermal_base + offset; in mtk_thermal_init_bank() local722 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); in mtk_thermal_init_bank()730 controller_base + TEMP_MONCTL2); in mtk_thermal_init_bank()734 controller_base + TEMP_AHBPOLL); in mtk_thermal_init_bank()737 writel(0x0, controller_base + TEMP_MSRCTL0); in mtk_thermal_init_bank()740 writel(0xffffffff, controller_base + TEMP_AHBTO); in mtk_thermal_init_bank()743 writel(0x0, controller_base + TEMP_MONIDET0); in mtk_thermal_init_bank()744 writel(0x0, controller_base + TEMP_MONIDET1); in mtk_thermal_init_bank()759 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); in mtk_thermal_init_bank()763 controller_base + TEMP_ADCMUXADDR); in mtk_thermal_init_bank()[all …]
133 void __iomem *controller_base; /* base of PCIe unit (not DW core) */ member147 return readl_relaxed(pcie->controller_base + offset); in al_pcie_controller_readl()153 writel_relaxed(val, pcie->controller_base + offset); in al_pcie_controller_writel()382 al_pcie->controller_base = devm_ioremap_resource(dev, controller_res); in al_pcie_probe()383 if (IS_ERR(al_pcie->controller_base)) { in al_pcie_probe()386 return PTR_ERR(al_pcie->controller_base); in al_pcie_probe()
