714 	void __iomem *controller_base = mt->thermal_base + offset;  in mtk_thermal_init_bank()  local
722 	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);  in mtk_thermal_init_bank()
730 			controller_base + TEMP_MONCTL2);  in mtk_thermal_init_bank()
734 	       controller_base + TEMP_AHBPOLL);  in mtk_thermal_init_bank()
737 	writel(0x0, controller_base + TEMP_MSRCTL0);  in mtk_thermal_init_bank()
740 	writel(0xffffffff, controller_base + TEMP_AHBTO);  in mtk_thermal_init_bank()
743 	writel(0x0, controller_base + TEMP_MONIDET0);  in mtk_thermal_init_bank()
744 	writel(0x0, controller_base + TEMP_MONIDET1);  in mtk_thermal_init_bank()
759 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);  in mtk_thermal_init_bank()
763 	       controller_base + TEMP_ADCMUXADDR);  in mtk_thermal_init_bank()
768 		       controller_base + TEMP_PNPMUXADDR);  in mtk_thermal_init_bank()
772 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);  in mtk_thermal_init_bank()
776 	       controller_base + TEMP_ADCENADDR);  in mtk_thermal_init_bank()
780 	       controller_base + TEMP_ADCVALIDADDR);  in mtk_thermal_init_bank()
784 	       controller_base + TEMP_ADCVOLTADDR);  in mtk_thermal_init_bank()
787 	writel(0x0, controller_base + TEMP_RDCTRL);  in mtk_thermal_init_bank()
791 	       controller_base + TEMP_ADCVALIDMASK);  in mtk_thermal_init_bank()
794 	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);  in mtk_thermal_init_bank()
798 		controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()
805 	       controller_base + TEMP_MONCTL0);  in mtk_thermal_init_bank()
809 	       controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()