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Searched refs:RREG32_SOC15 (Results 1 – 25 of 59) sorted by relevance

123

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dsmu_v11_0_i2c.c53 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); in smu_v11_0_i2c_set_clock_gating()
72 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); in smu_v11_0_i2c_clear_status()
140 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_tx_status()
148 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); in smu_v11_0_i2c_poll_tx_status()
151 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); in smu_v11_0_i2c_poll_tx_status()
182 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); in smu_v11_0_i2c_poll_rx_status()
201 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_rx_status()
252 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_transmit()
278 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_transmit()
378 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); in smu_v11_0_i2c_receive()
[all …]
Dmmhub_v2_0.c225 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
236 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
262 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_init_cache_regs()
275 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_0_init_cache_regs()
306 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_enable_system_domain()
429 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
436 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_gart_disable()
458 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_0_set_fault_enable_default()
546 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); in mmhub_v2_0_update_medium_grain_clock_gating()
547 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); in mmhub_v2_0_update_medium_grain_clock_gating()
[all …]
Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
86 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
91 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
107 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
Dnavi10_ih.c66 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); in force_update_wptr_for_self_int()
67 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
77 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in force_update_wptr_for_self_int()
93 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_enable_interrupts()
109 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_enable_interrupts()
125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in navi10_ih_enable_interrupts()
150 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_disable_interrupts()
170 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_disable_interrupts()
190 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in navi10_ih_disable_interrupts()
259 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); in navi10_ih_reroute_ih()
[all …]
Dvcn_v1_0.c236 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) in vcn_v1_0_hw_fini()
443 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
454 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
459 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
469 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
492 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
516 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
543 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
570 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
579 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_enable_clock_gating()
[all …]
Djpeg_v3_0.c52 u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); in jpeg_v3_0_early_init()
166 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) in jpeg_v3_0_hw_fini()
220 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v3_0_disable_clock_gating()
230 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_disable_clock_gating()
238 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v3_0_disable_clock_gating()
250 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_enable_clock_gating()
364 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_start()
409 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v3_0_dec_ring_get_rptr()
426 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_dec_ring_get_wptr()
453 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & in jpeg_v3_0_is_idle()
Dmmhub_v1_0.c39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
130 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
141 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
165 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
202 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
352 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_gart_disable()
362 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_gart_disable()
382 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v1_0_set_fault_enable_default()
[all …]
Dvcn_v3_0.c97 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); in vcn_v3_0_early_init()
360 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
597 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_disable_static_power_gating()
612 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_enable_static_power_gating()
664 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
673 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
699 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
722 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
756 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); in vcn_v3_0_disable_clock_gating()
764 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
[all …]
Dathub_v2_0.c40 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_update_medium_grain_clock_gating()
57 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_update_medium_grain_light_sleep()
96 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_0_get_clockgating()
Dathub_v2_1.c39 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_update_medium_grain_clock_gating()
56 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_update_medium_grain_light_sleep()
94 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v2_1_get_clockgating()
Dvcn_v2_0.c267 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
490 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
499 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
522 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
546 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
573 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
651 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
660 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
683 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
737 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_disable_static_power_gating()
[all …]
Dathub_v1_0.c37 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_update_medium_grain_clock_gating()
53 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_update_medium_grain_light_sleep()
97 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); in athub_v1_0_get_clockgating()
Dmes_v10_1.c420 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
429 data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); in mes_v10_1_enable()
438 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); in mes_v10_1_enable()
500 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid); in mes_v10_1_load_microcode()
503 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); in mes_v10_1_load_microcode()
520 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid); in mes_v10_1_load_microcode()
523 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); in mes_v10_1_load_microcode()
614 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); in mes_v10_1_mqd_init()
621 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in mes_v10_1_mqd_init()
651 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in mes_v10_1_mqd_init()
[all …]
Dvega10_ih.c49 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_enable_interrupts()
64 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_enable_interrupts()
80 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_enable_interrupts()
105 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_disable_interrupts()
125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_disable_interrupts()
145 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_disable_interrupts()
236 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_irq_init()
252 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); in vega10_ih_irq_init()
282 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_irq_init()
312 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_irq_init()
[all …]
Djpeg_v2_5.c63 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); in jpeg_v2_5_early_init()
199 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) in jpeg_v2_5_hw_fini()
254 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
264 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_disable_clock_gating()
271 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
283 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_enable_clock_gating()
341 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_start()
389 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); in jpeg_v2_5_dec_ring_get_rptr()
406 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_dec_ring_get_wptr()
437 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & in jpeg_v2_5_is_idle()
Dvcn_v2_5.c87 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); in vcn_v2_5_early_init()
330 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
553 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
562 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
588 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
612 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
639 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
718 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
727 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
749 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
[all …]
Dgfxhub_v2_1.c107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
190 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
216 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
229 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
260 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_1_enable_system_domain()
391 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_gart_disable()
419 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_set_fault_enable_default()
501 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); in gfxhub_v2_1_get_xgmi_info()
528 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), in gfxhub_v2_1_get_xgmi_info()
Dnbio_v7_4.c68 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v7_4_get_rev_id()
96 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); in nbio_v7_4_get_memsize()
184 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); in nbio_v7_4_ih_doorbell_range()
244 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v7_4_ih_control()
307 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
356 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
381 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); in nbio_v7_4_set_ras_controller_irq_state()
417 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); in nbio_v7_4_set_ras_err_event_athub_irq_state()
Dnbio_v7_0.c46 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v7_0_get_rev_id()
74 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); in nbio_v7_0_get_memsize()
129 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); in nbio_v7_0_ih_doorbell_range()
145 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); in nbio_7_0_read_syshub_ind_mmr()
238 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v7_0_ih_control()
Dgfxhub_v2_0.c107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_0_get_fb_location()
117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_0_get_mc_fb_offset()
192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
216 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
229 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_0_init_cache_regs()
260 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_0_enable_system_domain()
373 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_gart_disable()
396 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_set_fault_enable_default()
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_thermal.c105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
267 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_percent()
278 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega10_fan_ctrl_set_fan_speed_percent()
326 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega10_fan_ctrl_set_fan_speed_rpm()
[all …]
Dvega20_thermal.c95 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
98 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
150 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_percent()
161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega20_fan_ctrl_set_fan_speed_percent()
204 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega20_fan_ctrl_set_fan_speed_rpm()
221 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); in vega20_thermal_get_temperature()
259 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega20_thermal_set_temperature_range()
Dvega20_baco.c50 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); in vega20_baco_get_capability()
64 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); in vega20_baco_get_state()
89 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); in vega20_baco_set_state()
Dsmu9_baco.c44 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); in smu9_baco_get_capability()
58 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); in smu9_baco_get_state()
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu9_smumgr.c73 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
82 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
170 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102); in smu9_get_argument()
172 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()

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