1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "athub_v1_0.h"
25
26 #include "athub/athub_1_0_offset.h"
27 #include "athub/athub_1_0_sh_mask.h"
28 #include "vega10_enum.h"
29
30 #include "soc15_common.h"
31
athub_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)32 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
33 bool enable)
34 {
35 uint32_t def, data;
36
37 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
38
39 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
40 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
41 else
42 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
43
44 if (def != data)
45 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
46 }
47
athub_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)48 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
49 bool enable)
50 {
51 uint32_t def, data;
52
53 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
54
55 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
56 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
57 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
58 else
59 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
60
61 if(def != data)
62 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
63 }
64
athub_v1_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)65 int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
66 enum amd_clockgating_state state)
67 {
68 if (amdgpu_sriov_vf(adev))
69 return 0;
70
71 switch (adev->asic_type) {
72 case CHIP_VEGA10:
73 case CHIP_VEGA12:
74 case CHIP_VEGA20:
75 case CHIP_RAVEN:
76 case CHIP_RENOIR:
77 athub_update_medium_grain_clock_gating(adev,
78 state == AMD_CG_STATE_GATE);
79 athub_update_medium_grain_light_sleep(adev,
80 state == AMD_CG_STATE_GATE);
81 break;
82 default:
83 break;
84 }
85
86 return 0;
87 }
88
athub_v1_0_get_clockgating(struct amdgpu_device * adev,u32 * flags)89 void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
90 {
91 int data;
92
93 if (amdgpu_sriov_vf(adev))
94 *flags = 0;
95
96 /* AMD_CG_SUPPORT_ATHUB_MGCG */
97 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
98 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
99 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
100
101 /* AMD_CG_SUPPORT_ATHUB_LS */
102 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
103 *flags |= AMD_CG_SUPPORT_ATHUB_LS;
104 }
105
