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Searched refs:PIPECONF (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/i915/gvt/
Ddisplay.c62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
349 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
Dhandlers.c2025 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2026 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2027 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2028 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
/Linux-v5.10/drivers/gpu/drm/i915/display/
Dicl_dsi.c996 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_enable_transcoder()
998 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_enable_transcoder()
1001 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_enable_transcoder()
1222 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_disable_transcoder()
1224 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_disable_transcoder()
1227 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_disable_transcoder()
1631 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_get_hw_state()
Dintel_color.c480 val = intel_de_read(dev_priv, PIPECONF(pipe)); in i9xx_color_commit()
483 intel_de_write(dev_priv, PIPECONF(pipe), val); in i9xx_color_commit()
493 val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_color_commit()
496 intel_de_write(dev_priv, PIPECONF(pipe), val); in ilk_color_commit()
Dintel_display.c1094 i915_reg_t reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in assert_pipe()
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_enable_pch_transcoder()
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
1882 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()
1923 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()
5493 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_pll_enable()
5563 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_disable()
5592 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_disable()
5921 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ilk_pch_enable()
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Dintel_crt.c697 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
Dintel_display_power.c1248 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1250 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1264 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1265 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
Dintel_dp.c5504 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_disable()
5512 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_disable()
5531 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_enable()
5539 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_enable()
7247 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); in intel_dp_set_drrs_state()
Dvlv_dsi.c1025 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
/Linux-v5.10/drivers/gpu/drm/i915/
Di915_reg.h5997 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) macro