1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35 #include "i915_drv.h"
36 #include "gvt.h"
37
get_edp_pipe(struct intel_vgpu * vgpu)38 static int get_edp_pipe(struct intel_vgpu *vgpu)
39 {
40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
41 int pipe = -1;
42
43 switch (data & TRANS_DDI_EDP_INPUT_MASK) {
44 case TRANS_DDI_EDP_INPUT_A_ON:
45 case TRANS_DDI_EDP_INPUT_A_ONOFF:
46 pipe = PIPE_A;
47 break;
48 case TRANS_DDI_EDP_INPUT_B_ONOFF:
49 pipe = PIPE_B;
50 break;
51 case TRANS_DDI_EDP_INPUT_C_ONOFF:
52 pipe = PIPE_C;
53 break;
54 }
55 return pipe;
56 }
57
edp_pipe_is_enabled(struct intel_vgpu * vgpu)58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59 {
60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
61
62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63 return 0;
64
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
66 return 0;
67 return 1;
68 }
69
pipe_is_enabled(struct intel_vgpu * vgpu,int pipe)70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
71 {
72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
73
74 if (drm_WARN_ON(&dev_priv->drm,
75 pipe < PIPE_A || pipe >= I915_MAX_PIPES))
76 return -EINVAL;
77
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
79 return 1;
80
81 if (edp_pipe_is_enabled(vgpu) &&
82 get_edp_pipe(vgpu) == pipe)
83 return 1;
84 return 0;
85 }
86
87 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
88 {
89 /* EDID with 1024x768 as its resolution */
90 /*Header*/
91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
92 /* Vendor & Product Identification */
93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
94 /* Version & Revision */
95 0x01, 0x04,
96 /* Basic Display Parameters & Features */
97 0xa5, 0x34, 0x20, 0x78, 0x23,
98 /* Color Characteristics */
99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
100 /* Established Timings: maximum resolution is 1024x768 */
101 0x21, 0x08, 0x00,
102 /* Standard Timings. All invalid */
103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
105 /* 18 Byte Data Blocks 1: invalid */
106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
108 /* 18 Byte Data Blocks 2: invalid */
109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
111 /* 18 Byte Data Blocks 3: invalid */
112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
114 /* 18 Byte Data Blocks 4: invalid */
115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
117 /* Extension Block Count */
118 0x00,
119 /* Checksum */
120 0xef,
121 },
122 {
123 /* EDID with 1920x1200 as its resolution */
124 /*Header*/
125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
126 /* Vendor & Product Identification */
127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
128 /* Version & Revision */
129 0x01, 0x04,
130 /* Basic Display Parameters & Features */
131 0xa5, 0x34, 0x20, 0x78, 0x23,
132 /* Color Characteristics */
133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
134 /* Established Timings: maximum resolution is 1024x768 */
135 0x21, 0x08, 0x00,
136 /*
137 * Standard Timings.
138 * below new resolutions can be supported:
139 * 1920x1080, 1280x720, 1280x960, 1280x1024,
140 * 1440x900, 1600x1200, 1680x1050
141 */
142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
144 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
147 /* 18 Byte Data Blocks 2: invalid */
148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
150 /* 18 Byte Data Blocks 3: invalid */
151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
153 /* 18 Byte Data Blocks 4: invalid */
154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
156 /* Extension Block Count */
157 0x00,
158 /* Checksum */
159 0x45,
160 },
161 };
162
163 #define DPCD_HEADER_SIZE 0xb
164
165 /* let the virtual display supports DP1.2 */
166 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
167 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
168 };
169
emulate_monitor_status_change(struct intel_vgpu * vgpu)170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
171 {
172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
173 int pipe;
174
175 if (IS_BROXTON(dev_priv)) {
176 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
177 BXT_DE_PORT_HP_DDIB |
178 BXT_DE_PORT_HP_DDIC);
179
180 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
181 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
182 BXT_DE_PORT_HP_DDIA;
183 }
184
185 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
186 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
187 BXT_DE_PORT_HP_DDIB;
188 }
189
190 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
191 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
192 BXT_DE_PORT_HP_DDIC;
193 }
194
195 return;
196 }
197
198 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
199 SDE_PORTC_HOTPLUG_CPT |
200 SDE_PORTD_HOTPLUG_CPT);
201
202 if (IS_SKYLAKE(dev_priv) ||
203 IS_KABYLAKE(dev_priv) ||
204 IS_COFFEELAKE(dev_priv) ||
205 IS_COMETLAKE(dev_priv)) {
206 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
207 SDE_PORTE_HOTPLUG_SPT);
208 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
209 SKL_FUSE_DOWNLOAD_STATUS |
210 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
211 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
212 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
213 /*
214 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
215 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
216 * TRANSCODER_A can be enabled. PORT_x depends on the input of
217 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
218 * so we fixed to DPLL0 here.
219 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
220 */
221 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
222 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
223 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
224 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
225 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
226 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
227 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
228 /*
229 * Golden M/N are calculated based on:
230 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
231 * DP link clk 1620 MHz and non-constant_n.
232 * TODO: calculate DP link symbol clk and stream clk m/n.
233 */
234 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
235 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
236 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
237 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
238 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
239 }
240
241 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
242 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
243 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
244 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
245 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
246 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
247 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
248 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
249 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
250 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
251 TRANS_DDI_PORT_MASK);
252 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
253 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
254 (PORT_B << TRANS_DDI_PORT_SHIFT) |
255 TRANS_DDI_FUNC_ENABLE);
256 if (IS_BROADWELL(dev_priv)) {
257 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
258 ~PORT_CLK_SEL_MASK;
259 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
260 PORT_CLK_SEL_LCPLL_810;
261 }
262 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
263 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
264 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
265 }
266
267 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
268 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
269 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
270 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
271 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
272 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
273 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
274 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
275 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
276 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
277 TRANS_DDI_PORT_MASK);
278 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
279 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
280 (PORT_C << TRANS_DDI_PORT_SHIFT) |
281 TRANS_DDI_FUNC_ENABLE);
282 if (IS_BROADWELL(dev_priv)) {
283 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
284 ~PORT_CLK_SEL_MASK;
285 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
286 PORT_CLK_SEL_LCPLL_810;
287 }
288 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
289 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
290 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
291 }
292
293 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
294 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
295 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
296 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
297 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
298 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
299 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
300 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
301 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
302 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
303 TRANS_DDI_PORT_MASK);
304 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
305 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
306 (PORT_D << TRANS_DDI_PORT_SHIFT) |
307 TRANS_DDI_FUNC_ENABLE);
308 if (IS_BROADWELL(dev_priv)) {
309 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
310 ~PORT_CLK_SEL_MASK;
311 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
312 PORT_CLK_SEL_LCPLL_810;
313 }
314 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
315 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
316 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
317 }
318
319 if ((IS_SKYLAKE(dev_priv) ||
320 IS_KABYLAKE(dev_priv) ||
321 IS_COFFEELAKE(dev_priv) ||
322 IS_COMETLAKE(dev_priv)) &&
323 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
324 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
325 }
326
327 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
328 if (IS_BROADWELL(dev_priv))
329 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
330 GEN8_PORT_DP_A_HOTPLUG;
331 else
332 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
333
334 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
335 }
336
337 /* Clear host CRT status, so guest couldn't detect this host CRT. */
338 if (IS_BROADWELL(dev_priv))
339 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
340
341 /* Disable Primary/Sprite/Cursor plane */
342 for_each_pipe(dev_priv, pipe) {
343 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
344 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
345 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
346 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
347 }
348
349 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
350 }
351
clean_virtual_dp_monitor(struct intel_vgpu * vgpu,int port_num)352 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
353 {
354 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
355
356 kfree(port->edid);
357 port->edid = NULL;
358
359 kfree(port->dpcd);
360 port->dpcd = NULL;
361 }
362
setup_virtual_dp_monitor(struct intel_vgpu * vgpu,int port_num,int type,unsigned int resolution)363 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
364 int type, unsigned int resolution)
365 {
366 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
367 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
368
369 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
370 return -EINVAL;
371
372 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
373 if (!port->edid)
374 return -ENOMEM;
375
376 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
377 if (!port->dpcd) {
378 kfree(port->edid);
379 return -ENOMEM;
380 }
381
382 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
383 EDID_SIZE);
384 port->edid->data_valid = true;
385
386 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
387 port->dpcd->data_valid = true;
388 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
389 port->type = type;
390 port->id = resolution;
391
392 emulate_monitor_status_change(vgpu);
393
394 return 0;
395 }
396
397 /**
398 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
399 * be turned on/off when a virtual pipe is enabled/disabled.
400 * @gvt: a GVT device
401 *
402 * This function is used to turn on/off vblank timer according to currently
403 * enabled/disabled virtual pipes.
404 *
405 */
intel_gvt_check_vblank_emulation(struct intel_gvt * gvt)406 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
407 {
408 struct intel_gvt_irq *irq = &gvt->irq;
409 struct intel_vgpu *vgpu;
410 int pipe, id;
411 int found = false;
412
413 mutex_lock(&gvt->lock);
414 for_each_active_vgpu(gvt, vgpu, id) {
415 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
416 if (pipe_is_enabled(vgpu, pipe)) {
417 found = true;
418 break;
419 }
420 }
421 if (found)
422 break;
423 }
424
425 /* all the pipes are disabled */
426 if (!found)
427 hrtimer_cancel(&irq->vblank_timer.timer);
428 else
429 hrtimer_start(&irq->vblank_timer.timer,
430 ktime_add_ns(ktime_get(), irq->vblank_timer.period),
431 HRTIMER_MODE_ABS);
432 mutex_unlock(&gvt->lock);
433 }
434
emulate_vblank_on_pipe(struct intel_vgpu * vgpu,int pipe)435 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
436 {
437 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
438 struct intel_vgpu_irq *irq = &vgpu->irq;
439 int vblank_event[] = {
440 [PIPE_A] = PIPE_A_VBLANK,
441 [PIPE_B] = PIPE_B_VBLANK,
442 [PIPE_C] = PIPE_C_VBLANK,
443 };
444 int event;
445
446 if (pipe < PIPE_A || pipe > PIPE_C)
447 return;
448
449 for_each_set_bit(event, irq->flip_done_event[pipe],
450 INTEL_GVT_EVENT_MAX) {
451 clear_bit(event, irq->flip_done_event[pipe]);
452 if (!pipe_is_enabled(vgpu, pipe))
453 continue;
454
455 intel_vgpu_trigger_virtual_event(vgpu, event);
456 }
457
458 if (pipe_is_enabled(vgpu, pipe)) {
459 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
460 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
461 }
462 }
463
emulate_vblank(struct intel_vgpu * vgpu)464 static void emulate_vblank(struct intel_vgpu *vgpu)
465 {
466 int pipe;
467
468 mutex_lock(&vgpu->vgpu_lock);
469 for_each_pipe(vgpu->gvt->gt->i915, pipe)
470 emulate_vblank_on_pipe(vgpu, pipe);
471 mutex_unlock(&vgpu->vgpu_lock);
472 }
473
474 /**
475 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
476 * @gvt: a GVT device
477 *
478 * This function is used to trigger vblank interrupts for vGPUs on GVT device
479 *
480 */
intel_gvt_emulate_vblank(struct intel_gvt * gvt)481 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
482 {
483 struct intel_vgpu *vgpu;
484 int id;
485
486 mutex_lock(&gvt->lock);
487 for_each_active_vgpu(gvt, vgpu, id)
488 emulate_vblank(vgpu);
489 mutex_unlock(&gvt->lock);
490 }
491
492 /**
493 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
494 * @vgpu: a vGPU
495 * @connected: link state
496 *
497 * This function is used to trigger hotplug interrupt for vGPU
498 *
499 */
intel_vgpu_emulate_hotplug(struct intel_vgpu * vgpu,bool connected)500 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
501 {
502 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
503
504 /* TODO: add more platforms support */
505 if (IS_SKYLAKE(i915) ||
506 IS_KABYLAKE(i915) ||
507 IS_COFFEELAKE(i915) ||
508 IS_COMETLAKE(i915)) {
509 if (connected) {
510 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
511 SFUSE_STRAP_DDID_DETECTED;
512 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
513 } else {
514 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
515 ~SFUSE_STRAP_DDID_DETECTED;
516 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
517 }
518 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
519 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
520 PORTD_HOTPLUG_STATUS_MASK;
521 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
522 }
523 }
524
525 /**
526 * intel_vgpu_clean_display - clean vGPU virtual display emulation
527 * @vgpu: a vGPU
528 *
529 * This function is used to clean vGPU virtual display emulation stuffs
530 *
531 */
intel_vgpu_clean_display(struct intel_vgpu * vgpu)532 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
533 {
534 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
535
536 if (IS_SKYLAKE(dev_priv) ||
537 IS_KABYLAKE(dev_priv) ||
538 IS_COFFEELAKE(dev_priv) ||
539 IS_COMETLAKE(dev_priv))
540 clean_virtual_dp_monitor(vgpu, PORT_D);
541 else
542 clean_virtual_dp_monitor(vgpu, PORT_B);
543 }
544
545 /**
546 * intel_vgpu_init_display- initialize vGPU virtual display emulation
547 * @vgpu: a vGPU
548 * @resolution: resolution index for intel_vgpu_edid
549 *
550 * This function is used to initialize vGPU virtual display emulation stuffs
551 *
552 * Returns:
553 * Zero on success, negative error code if failed.
554 *
555 */
intel_vgpu_init_display(struct intel_vgpu * vgpu,u64 resolution)556 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
557 {
558 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
559
560 intel_vgpu_init_i2c_edid(vgpu);
561
562 if (IS_SKYLAKE(dev_priv) ||
563 IS_KABYLAKE(dev_priv) ||
564 IS_COFFEELAKE(dev_priv) ||
565 IS_COMETLAKE(dev_priv))
566 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
567 resolution);
568 else
569 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
570 resolution);
571 }
572
573 /**
574 * intel_vgpu_reset_display- reset vGPU virtual display emulation
575 * @vgpu: a vGPU
576 *
577 * This function is used to reset vGPU virtual display emulation stuffs
578 *
579 */
intel_vgpu_reset_display(struct intel_vgpu * vgpu)580 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
581 {
582 emulate_monitor_status_change(vgpu);
583 }
584
