Searched refs:ttbr (Results 1 – 13 of 13) sorted by relevance
| /Linux-v4.19/arch/arm64/include/asm/ |
| D | mmu_context.h | 52 unsigned long ttbr = phys_to_ttbr(__pa_symbol(empty_zero_page)); in cpu_set_reserved_ttbr0() local
54 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0()
177 u64 ttbr; in update_saved_ttbr0() local
183 ttbr = __pa_symbol(empty_zero_page); in update_saved_ttbr0()
185 ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; in update_saved_ttbr0()
187 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| D | uaccess.h | 122 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
125 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
126 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
128 write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1); in __uaccess_ttbr0_disable()
131 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| D | assembler.h | 526 .macro phys_to_ttbr, ttbr, phys
528 orr \ttbr, \phys, \phys, lsr #46
529 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
531 mov \ttbr, \phys
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| /Linux-v4.19/arch/arm/include/asm/ |
| D | proc-fns.h | 126 u64 ttbr; \
128 : "=r" (ttbr)); \
129 ttbr; \
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| /Linux-v4.19/drivers/iommu/ |
| D | io-pgtable.h | 90 u64 ttbr[2]; member
101 u32 ttbr[2]; member
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| D | arm-smmu.c | 142 u64 ttbr[2]; member
612 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0]; in arm_smmu_init_context_bank()
613 cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1]; in arm_smmu_init_context_bank()
615 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; in arm_smmu_init_context_bank()
616 cb->ttbr[0] |= (u64)cfg->asid << TTBRn_ASID_SHIFT; in arm_smmu_init_context_bank()
617 cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; in arm_smmu_init_context_bank()
618 cb->ttbr[1] |= (u64)cfg->asid << TTBRn_ASID_SHIFT; in arm_smmu_init_context_bank()
621 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
698 writel_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0); in arm_smmu_write_context_bank()
699 writel_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1); in arm_smmu_write_context_bank()
[all …]
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| D | ipmmu-vmsa.c | 409 u64 ttbr; in ipmmu_domain_init_context() local
455 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; in ipmmu_domain_init_context()
456 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_init_context()
457 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_init_context()
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| D | mtk_iommu.c | 347 writel(dom->cfg.arm_v7s_cfg.ttbr[0], in mtk_iommu_attach_device()
727 writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0], in mtk_iommu_resume()
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| D | qcom_iommu.c | 260 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | in qcom_iommu_init_domain()
263 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | in qcom_iommu_init_domain()
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| D | io-pgtable-arm-v7s.c | 775 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | in arm_v7s_alloc_pgtable()
779 cfg->arm_v7s_cfg.ttbr[1] = 0; in arm_v7s_alloc_pgtable()
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| D | msm_iommu.c | 284 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); in __program_context()
285 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); in __program_context()
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| D | io-pgtable-arm.c | 851 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()
852 cfg->arm_lpae_s1_cfg.ttbr[1] = 0; in arm_64_lpae_alloc_pgtable_s1()
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| D | arm-smmu-v3.c | 503 u64 ttbr; member
1037 val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK; in arm_smmu_write_ctx_desc()
1547 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; in arm_smmu_domain_finalise_s1()
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