Home
last modified time | relevance | path

Searched refs:tiling (Results 1 – 25 of 25) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/
Di915_gem_tiling.c72 u32 size, unsigned int tiling, unsigned int stride) in i915_gem_fence_size() argument
78 if (tiling == I915_TILING_NONE) in i915_gem_fence_size()
84 stride *= i915_gem_tile_height(tiling); in i915_gem_fence_size()
112 unsigned int tiling, unsigned int stride) in i915_gem_fence_alignment() argument
120 if (tiling == I915_TILING_NONE) in i915_gem_fence_alignment()
130 return i915_gem_fence_size(i915, size, tiling, stride); in i915_gem_fence_alignment()
136 unsigned int tiling, unsigned int stride) in i915_tiling_ok() argument
142 if (tiling == I915_TILING_NONE) in i915_tiling_ok()
145 if (tiling > I915_TILING_LAST) in i915_tiling_ok()
166 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) in i915_tiling_ok()
[all …]
Di915_gem_object.h442 i915_gem_tile_height(unsigned int tiling) in i915_gem_tile_height() argument
444 GEM_BUG_ON(!tiling); in i915_gem_tile_height()
445 return tiling == I915_TILING_Y ? 32 : 8; in i915_gem_tile_height()
462 unsigned int tiling, unsigned int stride);
Di915_gem_fence_reg.c123 unsigned int tiling = i915_gem_object_get_tiling(vma->obj); in i915_write_fence_reg() local
124 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
Di915_gpu_error.h186 u32 tiling:2; member
Di915_gpu_error.c60 static const char *tiling_flag(int tiling) in tiling_flag() argument
62 switch (tiling) { in tiling_flag()
387 err_puts(m, tiling_flag(err->tiling)); in print_error_buffers()
1042 err->tiling = i915_gem_object_get_tiling(obj); in capture_bo()
Dintel_display.c2724 if (plane_config->tiling == I915_TILING_X) in intel_alloc_initial_plane_obj()
7750 plane_config->tiling = I915_TILING_X; in i9xx_get_initial_plane_config()
7763 if (plane_config->tiling) in i9xx_get_initial_plane_config()
8757 u32 val, base, offset, stride_mult, tiling, alpha; in skylake_get_initial_plane_config() local
8796 tiling = val & PLANE_CTL_TILED_MASK; in skylake_get_initial_plane_config()
8797 switch (tiling) { in skylake_get_initial_plane_config()
8802 plane_config->tiling = I915_TILING_X; in skylake_get_initial_plane_config()
8818 MISSING_CASE(tiling); in skylake_get_initial_plane_config()
14412 unsigned int tiling, stride; in intel_framebuffer_init() local
14418 tiling = i915_gem_object_get_tiling(obj); in intel_framebuffer_init()
[all …]
Di915_drv.h3318 unsigned int tiling, unsigned int stride);
3320 unsigned int tiling, unsigned int stride);
Dintel_drv.h544 unsigned int tiling; member
/Linux-v4.19/drivers/gpu/drm/tegra/
Dfb.c43 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling() argument
49 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
50 tiling->value = 0; in tegra_fb_get_tiling()
54 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
55 tiling->value = 0; in tegra_fb_get_tiling()
59 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
60 tiling->value = 0; in tegra_fb_get_tiling()
64 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
65 tiling->value = 1; in tegra_fb_get_tiling()
69 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
[all …]
Dhub.c333 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
347 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_shared_plane_atomic_check()
351 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
492 unsigned long height = state->tiling.value; in tegra_shared_plane_atomic_update()
495 switch (state->tiling.mode) { in tegra_shared_plane_atomic_update()
Dplane.h45 struct tegra_bo_tiling tiling; member
Dgem.h47 struct tegra_bo_tiling tiling; member
Dplane.c56 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
Ddc.c409 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
411 switch (window->tiling.mode) { in tegra_dc_setup_window()
428 switch (window->tiling.mode) { in tegra_dc_setup_window()
600 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check() local
627 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_plane_atomic_check()
631 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
708 window.tiling = state->tiling; in tegra_plane_atomic_update()
Ddrm.h181 struct tegra_bo_tiling *tiling);
Ddrm.c786 bo->tiling.mode = mode; in tegra_gem_set_tiling()
787 bo->tiling.value = value; in tegra_gem_set_tiling()
808 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
821 args->value = bo->tiling.value; in tegra_gem_get_tiling()
Ddc.h146 struct tegra_bo_tiling tiling; member
Dgem.c295 bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED; in tegra_bo_create()
/Linux-v4.19/drivers/gpu/drm/i915/selftests/
Di915_gem_object.c149 unsigned int tiling; member
162 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
168 if (tile->tiling == I915_TILING_X) { in tiled_offset()
218 __func__, tile->tiling, tile->stride)) in check_partial_mapping()
221 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mapping()
224 tile->tiling, tile->stride, err); in check_partial_mapping()
228 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); in check_partial_mapping()
286 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride, in check_partial_mapping()
310 int tiling; in igt_partial_tiling() local
346 tile.tiling = I915_TILING_NONE; in igt_partial_tiling()
[all …]
/Linux-v4.19/drivers/gpu/drm/vc4/
Dvc4_render_cl.c441 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup() local
492 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_surface_setup()
526 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
540 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup() local
569 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_render_config_surface_setup()
587 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()
Dvc4_plane.c474 u32 lbm_size, tiling; in vc4_plane_mode_set() local
518 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
531 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
561 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
564 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
567 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
594 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dml/
Ddml1_display_rq_dlg_calc.c371 int tiling, in dml1_rq_dlg_get_row_heights() argument
376 bool surf_linear = (tiling == dm_sw_linear); in dml1_rq_dlg_get_row_heights()
427 if (tiling != dm_sw_linear) in dml1_rq_dlg_get_row_heights()
/Linux-v4.19/Documentation/gpu/
Di915.rst413 :doc: tiling swizzling details
422 :doc: buffer object tiling
/Linux-v4.19/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
Dcom.fuc518 // to correctly handle tiling.
/Linux-v4.19/Documentation/media/uapi/v4l/
Dbuffer.rst48 pixel format, the line stride, the tiling orientation or the rotation) is