1 /*
2 * Copyright © 2014-2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * DOC: Render command list generation
26 *
27 * In the V3D hardware, render command lists are what load and store
28 * tiles of a framebuffer and optionally call out to binner-generated
29 * command lists to do the 3D drawing for that tile.
30 *
31 * In the VC4 driver, render command list generation is performed by the
32 * kernel instead of userspace. We do this because validating a
33 * user-submitted command list is hard to get right and has high CPU overhead,
34 * while the number of valid configurations for render command lists is
35 * actually fairly low.
36 */
37
38 #include "uapi/drm/vc4_drm.h"
39 #include "vc4_drv.h"
40 #include "vc4_packet.h"
41
42 struct vc4_rcl_setup {
43 struct drm_gem_cma_object *color_read;
44 struct drm_gem_cma_object *color_write;
45 struct drm_gem_cma_object *zs_read;
46 struct drm_gem_cma_object *zs_write;
47 struct drm_gem_cma_object *msaa_color_write;
48 struct drm_gem_cma_object *msaa_zs_write;
49
50 struct drm_gem_cma_object *rcl;
51 u32 next_offset;
52
53 u32 next_write_bo_index;
54 };
55
rcl_u8(struct vc4_rcl_setup * setup,u8 val)56 static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
57 {
58 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val;
59 setup->next_offset += 1;
60 }
61
rcl_u16(struct vc4_rcl_setup * setup,u16 val)62 static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val)
63 {
64 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val;
65 setup->next_offset += 2;
66 }
67
rcl_u32(struct vc4_rcl_setup * setup,u32 val)68 static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val)
69 {
70 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val;
71 setup->next_offset += 4;
72 }
73
74 /*
75 * Emits a no-op STORE_TILE_BUFFER_GENERAL.
76 *
77 * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
78 * some sort before another load is triggered.
79 */
vc4_store_before_load(struct vc4_rcl_setup * setup)80 static void vc4_store_before_load(struct vc4_rcl_setup *setup)
81 {
82 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
83 rcl_u16(setup,
84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE,
85 VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
86 VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
87 VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
88 VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR);
89 rcl_u32(setup, 0); /* no address, since we're in None mode */
90 }
91
92 /*
93 * Calculates the physical address of the start of a tile in a RCL surface.
94 *
95 * Unlike the other load/store packets,
96 * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile
97 * coordinates packet, and instead just store to the address given.
98 */
vc4_full_res_offset(struct vc4_exec_info * exec,struct drm_gem_cma_object * bo,struct drm_vc4_submit_rcl_surface * surf,uint8_t x,uint8_t y)99 static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec,
100 struct drm_gem_cma_object *bo,
101 struct drm_vc4_submit_rcl_surface *surf,
102 uint8_t x, uint8_t y)
103 {
104 return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE *
105 (DIV_ROUND_UP(exec->args->width, 32) * y + x);
106 }
107
108 /*
109 * Emits a PACKET_TILE_COORDINATES if one isn't already pending.
110 *
111 * The tile coordinates packet triggers a pending load if there is one, are
112 * used for clipping during rendering, and determine where loads/stores happen
113 * relative to their base address.
114 */
vc4_tile_coordinates(struct vc4_rcl_setup * setup,uint32_t x,uint32_t y)115 static void vc4_tile_coordinates(struct vc4_rcl_setup *setup,
116 uint32_t x, uint32_t y)
117 {
118 rcl_u8(setup, VC4_PACKET_TILE_COORDINATES);
119 rcl_u8(setup, x);
120 rcl_u8(setup, y);
121 }
122
emit_tile(struct vc4_exec_info * exec,struct vc4_rcl_setup * setup,uint8_t x,uint8_t y,bool first,bool last)123 static void emit_tile(struct vc4_exec_info *exec,
124 struct vc4_rcl_setup *setup,
125 uint8_t x, uint8_t y, bool first, bool last)
126 {
127 struct drm_vc4_submit_cl *args = exec->args;
128 bool has_bin = args->bin_cl_size != 0;
129
130 /* Note that the load doesn't actually occur until the
131 * tile coords packet is processed, and only one load
132 * may be outstanding at a time.
133 */
134 if (setup->color_read) {
135 if (args->color_read.flags &
136 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
137 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
138 rcl_u32(setup,
139 vc4_full_res_offset(exec, setup->color_read,
140 &args->color_read, x, y) |
141 VC4_LOADSTORE_FULL_RES_DISABLE_ZS);
142 } else {
143 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
144 rcl_u16(setup, args->color_read.bits);
145 rcl_u32(setup, setup->color_read->paddr +
146 args->color_read.offset);
147 }
148 }
149
150 if (setup->zs_read) {
151 if (args->zs_read.flags &
152 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
153 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
154 rcl_u32(setup,
155 vc4_full_res_offset(exec, setup->zs_read,
156 &args->zs_read, x, y) |
157 VC4_LOADSTORE_FULL_RES_DISABLE_COLOR);
158 } else {
159 if (setup->color_read) {
160 /* Exec previous load. */
161 vc4_tile_coordinates(setup, x, y);
162 vc4_store_before_load(setup);
163 }
164
165 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
166 rcl_u16(setup, args->zs_read.bits);
167 rcl_u32(setup, setup->zs_read->paddr +
168 args->zs_read.offset);
169 }
170 }
171
172 /* Clipping depends on tile coordinates having been
173 * emitted, so we always need one here.
174 */
175 vc4_tile_coordinates(setup, x, y);
176
177 /* Wait for the binner before jumping to the first
178 * tile's lists.
179 */
180 if (first && has_bin)
181 rcl_u8(setup, VC4_PACKET_WAIT_ON_SEMAPHORE);
182
183 if (has_bin) {
184 rcl_u8(setup, VC4_PACKET_BRANCH_TO_SUB_LIST);
185 rcl_u32(setup, (exec->tile_alloc_offset +
186 (y * exec->bin_tiles_x + x) * 32));
187 }
188
189 if (setup->msaa_color_write) {
190 bool last_tile_write = (!setup->msaa_zs_write &&
191 !setup->zs_write &&
192 !setup->color_write);
193 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS;
194
195 if (!last_tile_write)
196 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
197 else if (last)
198 bits |= VC4_LOADSTORE_FULL_RES_EOF;
199 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
200 rcl_u32(setup,
201 vc4_full_res_offset(exec, setup->msaa_color_write,
202 &args->msaa_color_write, x, y) |
203 bits);
204 }
205
206 if (setup->msaa_zs_write) {
207 bool last_tile_write = (!setup->zs_write &&
208 !setup->color_write);
209 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR;
210
211 if (setup->msaa_color_write)
212 vc4_tile_coordinates(setup, x, y);
213 if (!last_tile_write)
214 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
215 else if (last)
216 bits |= VC4_LOADSTORE_FULL_RES_EOF;
217 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
218 rcl_u32(setup,
219 vc4_full_res_offset(exec, setup->msaa_zs_write,
220 &args->msaa_zs_write, x, y) |
221 bits);
222 }
223
224 if (setup->zs_write) {
225 bool last_tile_write = !setup->color_write;
226
227 if (setup->msaa_color_write || setup->msaa_zs_write)
228 vc4_tile_coordinates(setup, x, y);
229
230 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
231 rcl_u16(setup, args->zs_write.bits |
232 (last_tile_write ?
233 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR));
234 rcl_u32(setup,
235 (setup->zs_write->paddr + args->zs_write.offset) |
236 ((last && last_tile_write) ?
237 VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
238 }
239
240 if (setup->color_write) {
241 if (setup->msaa_color_write || setup->msaa_zs_write ||
242 setup->zs_write) {
243 vc4_tile_coordinates(setup, x, y);
244 }
245
246 if (last)
247 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
248 else
249 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER);
250 }
251 }
252
vc4_create_rcl_bo(struct drm_device * dev,struct vc4_exec_info * exec,struct vc4_rcl_setup * setup)253 static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
254 struct vc4_rcl_setup *setup)
255 {
256 struct drm_vc4_submit_cl *args = exec->args;
257 bool has_bin = args->bin_cl_size != 0;
258 uint8_t min_x_tile = args->min_x_tile;
259 uint8_t min_y_tile = args->min_y_tile;
260 uint8_t max_x_tile = args->max_x_tile;
261 uint8_t max_y_tile = args->max_y_tile;
262 uint8_t xtiles = max_x_tile - min_x_tile + 1;
263 uint8_t ytiles = max_y_tile - min_y_tile + 1;
264 uint8_t xi, yi;
265 uint32_t size, loop_body_size;
266 bool positive_x = true;
267 bool positive_y = true;
268
269 if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) {
270 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X))
271 positive_x = false;
272 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y))
273 positive_y = false;
274 }
275
276 size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE;
277 loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE;
278
279 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
280 size += VC4_PACKET_CLEAR_COLORS_SIZE +
281 VC4_PACKET_TILE_COORDINATES_SIZE +
282 VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
283 }
284
285 if (setup->color_read) {
286 if (args->color_read.flags &
287 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
288 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
289 } else {
290 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
291 }
292 }
293 if (setup->zs_read) {
294 if (args->zs_read.flags &
295 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
296 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
297 } else {
298 if (setup->color_read &&
299 !(args->color_read.flags &
300 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) {
301 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
302 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
303 }
304 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
305 }
306 }
307
308 if (has_bin) {
309 size += VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE;
310 loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE;
311 }
312
313 if (setup->msaa_color_write)
314 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
315 if (setup->msaa_zs_write)
316 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
317
318 if (setup->zs_write)
319 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
320 if (setup->color_write)
321 loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE;
322
323 /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */
324 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE *
325 ((setup->msaa_color_write != NULL) +
326 (setup->msaa_zs_write != NULL) +
327 (setup->color_write != NULL) +
328 (setup->zs_write != NULL) - 1);
329
330 size += xtiles * ytiles * loop_body_size;
331
332 setup->rcl = &vc4_bo_create(dev, size, true, VC4_BO_TYPE_RCL)->base;
333 if (IS_ERR(setup->rcl))
334 return PTR_ERR(setup->rcl);
335 list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head,
336 &exec->unref_list);
337
338 /* The tile buffer gets cleared when the previous tile is stored. If
339 * the clear values changed between frames, then the tile buffer has
340 * stale clear values in it, so we have to do a store in None mode (no
341 * writes) so that we trigger the tile buffer clear.
342 */
343 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
344 rcl_u8(setup, VC4_PACKET_CLEAR_COLORS);
345 rcl_u32(setup, args->clear_color[0]);
346 rcl_u32(setup, args->clear_color[1]);
347 rcl_u32(setup, args->clear_z);
348 rcl_u8(setup, args->clear_s);
349
350 vc4_tile_coordinates(setup, 0, 0);
351
352 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
353 rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE);
354 rcl_u32(setup, 0); /* no address, since we're in None mode */
355 }
356
357 rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
358 rcl_u32(setup,
359 (setup->color_write ? (setup->color_write->paddr +
360 args->color_write.offset) :
361 0));
362 rcl_u16(setup, args->width);
363 rcl_u16(setup, args->height);
364 rcl_u16(setup, args->color_write.bits);
365
366 for (yi = 0; yi < ytiles; yi++) {
367 int y = positive_y ? min_y_tile + yi : max_y_tile - yi;
368 for (xi = 0; xi < xtiles; xi++) {
369 int x = positive_x ? min_x_tile + xi : max_x_tile - xi;
370 bool first = (xi == 0 && yi == 0);
371 bool last = (xi == xtiles - 1 && yi == ytiles - 1);
372
373 emit_tile(exec, setup, x, y, first, last);
374 }
375 }
376
377 BUG_ON(setup->next_offset != size);
378 exec->ct1ca = setup->rcl->paddr;
379 exec->ct1ea = setup->rcl->paddr + setup->next_offset;
380
381 return 0;
382 }
383
vc4_full_res_bounds_check(struct vc4_exec_info * exec,struct drm_gem_cma_object * obj,struct drm_vc4_submit_rcl_surface * surf)384 static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
385 struct drm_gem_cma_object *obj,
386 struct drm_vc4_submit_rcl_surface *surf)
387 {
388 struct drm_vc4_submit_cl *args = exec->args;
389 u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32);
390
391 if (surf->offset > obj->base.size) {
392 DRM_DEBUG("surface offset %d > BO size %zd\n",
393 surf->offset, obj->base.size);
394 return -EINVAL;
395 }
396
397 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
398 render_tiles_stride * args->max_y_tile + args->max_x_tile) {
399 DRM_DEBUG("MSAA tile %d, %d out of bounds "
400 "(bo size %zd, offset %d).\n",
401 args->max_x_tile, args->max_y_tile,
402 obj->base.size,
403 surf->offset);
404 return -EINVAL;
405 }
406
407 return 0;
408 }
409
vc4_rcl_msaa_surface_setup(struct vc4_exec_info * exec,struct drm_gem_cma_object ** obj,struct drm_vc4_submit_rcl_surface * surf)410 static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
411 struct drm_gem_cma_object **obj,
412 struct drm_vc4_submit_rcl_surface *surf)
413 {
414 if (surf->flags != 0 || surf->bits != 0) {
415 DRM_DEBUG("MSAA surface had nonzero flags/bits\n");
416 return -EINVAL;
417 }
418
419 if (surf->hindex == ~0)
420 return 0;
421
422 *obj = vc4_use_bo(exec, surf->hindex);
423 if (!*obj)
424 return -EINVAL;
425
426 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
427
428 if (surf->offset & 0xf) {
429 DRM_DEBUG("MSAA write must be 16b aligned.\n");
430 return -EINVAL;
431 }
432
433 return vc4_full_res_bounds_check(exec, *obj, surf);
434 }
435
vc4_rcl_surface_setup(struct vc4_exec_info * exec,struct drm_gem_cma_object ** obj,struct drm_vc4_submit_rcl_surface * surf,bool is_write)436 static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
437 struct drm_gem_cma_object **obj,
438 struct drm_vc4_submit_rcl_surface *surf,
439 bool is_write)
440 {
441 uint8_t tiling = VC4_GET_FIELD(surf->bits,
442 VC4_LOADSTORE_TILE_BUFFER_TILING);
443 uint8_t buffer = VC4_GET_FIELD(surf->bits,
444 VC4_LOADSTORE_TILE_BUFFER_BUFFER);
445 uint8_t format = VC4_GET_FIELD(surf->bits,
446 VC4_LOADSTORE_TILE_BUFFER_FORMAT);
447 int cpp;
448 int ret;
449
450 if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
451 DRM_DEBUG("Extra flags set\n");
452 return -EINVAL;
453 }
454
455 if (surf->hindex == ~0)
456 return 0;
457
458 *obj = vc4_use_bo(exec, surf->hindex);
459 if (!*obj)
460 return -EINVAL;
461
462 if (is_write)
463 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
464
465 if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
466 if (surf == &exec->args->zs_write) {
467 DRM_DEBUG("general zs write may not be a full-res.\n");
468 return -EINVAL;
469 }
470
471 if (surf->bits != 0) {
472 DRM_DEBUG("load/store general bits set with "
473 "full res load/store.\n");
474 return -EINVAL;
475 }
476
477 ret = vc4_full_res_bounds_check(exec, *obj, surf);
478 if (ret)
479 return ret;
480
481 return 0;
482 }
483
484 if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
485 VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
486 VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
487 DRM_DEBUG("Unknown bits in load/store: 0x%04x\n",
488 surf->bits);
489 return -EINVAL;
490 }
491
492 if (tiling > VC4_TILING_FORMAT_LT) {
493 DRM_DEBUG("Bad tiling format\n");
494 return -EINVAL;
495 }
496
497 if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) {
498 if (format != 0) {
499 DRM_DEBUG("No color format should be set for ZS\n");
500 return -EINVAL;
501 }
502 cpp = 4;
503 } else if (buffer == VC4_LOADSTORE_TILE_BUFFER_COLOR) {
504 switch (format) {
505 case VC4_LOADSTORE_TILE_BUFFER_BGR565:
506 case VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER:
507 cpp = 2;
508 break;
509 case VC4_LOADSTORE_TILE_BUFFER_RGBA8888:
510 cpp = 4;
511 break;
512 default:
513 DRM_DEBUG("Bad tile buffer format\n");
514 return -EINVAL;
515 }
516 } else {
517 DRM_DEBUG("Bad load/store buffer %d.\n", buffer);
518 return -EINVAL;
519 }
520
521 if (surf->offset & 0xf) {
522 DRM_DEBUG("load/store buffer must be 16b aligned.\n");
523 return -EINVAL;
524 }
525
526 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
527 exec->args->width, exec->args->height, cpp)) {
528 return -EINVAL;
529 }
530
531 return 0;
532 }
533
534 static int
vc4_rcl_render_config_surface_setup(struct vc4_exec_info * exec,struct vc4_rcl_setup * setup,struct drm_gem_cma_object ** obj,struct drm_vc4_submit_rcl_surface * surf)535 vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
536 struct vc4_rcl_setup *setup,
537 struct drm_gem_cma_object **obj,
538 struct drm_vc4_submit_rcl_surface *surf)
539 {
540 uint8_t tiling = VC4_GET_FIELD(surf->bits,
541 VC4_RENDER_CONFIG_MEMORY_FORMAT);
542 uint8_t format = VC4_GET_FIELD(surf->bits,
543 VC4_RENDER_CONFIG_FORMAT);
544 int cpp;
545
546 if (surf->flags != 0) {
547 DRM_DEBUG("No flags supported on render config.\n");
548 return -EINVAL;
549 }
550
551 if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK |
552 VC4_RENDER_CONFIG_FORMAT_MASK |
553 VC4_RENDER_CONFIG_MS_MODE_4X |
554 VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
555 DRM_DEBUG("Unknown bits in render config: 0x%04x\n",
556 surf->bits);
557 return -EINVAL;
558 }
559
560 if (surf->hindex == ~0)
561 return 0;
562
563 *obj = vc4_use_bo(exec, surf->hindex);
564 if (!*obj)
565 return -EINVAL;
566
567 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
568
569 if (tiling > VC4_TILING_FORMAT_LT) {
570 DRM_DEBUG("Bad tiling format\n");
571 return -EINVAL;
572 }
573
574 switch (format) {
575 case VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED:
576 case VC4_RENDER_CONFIG_FORMAT_BGR565:
577 cpp = 2;
578 break;
579 case VC4_RENDER_CONFIG_FORMAT_RGBA8888:
580 cpp = 4;
581 break;
582 default:
583 DRM_DEBUG("Bad tile buffer format\n");
584 return -EINVAL;
585 }
586
587 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
588 exec->args->width, exec->args->height, cpp)) {
589 return -EINVAL;
590 }
591
592 return 0;
593 }
594
vc4_get_rcl(struct drm_device * dev,struct vc4_exec_info * exec)595 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
596 {
597 struct vc4_rcl_setup setup = {0};
598 struct drm_vc4_submit_cl *args = exec->args;
599 bool has_bin = args->bin_cl_size != 0;
600 int ret;
601
602 if (args->min_x_tile > args->max_x_tile ||
603 args->min_y_tile > args->max_y_tile) {
604 DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
605 args->min_x_tile, args->min_y_tile,
606 args->max_x_tile, args->max_y_tile);
607 return -EINVAL;
608 }
609
610 if (has_bin &&
611 (args->max_x_tile > exec->bin_tiles_x ||
612 args->max_y_tile > exec->bin_tiles_y)) {
613 DRM_DEBUG("Render tiles (%d,%d) outside of bin config "
614 "(%d,%d)\n",
615 args->max_x_tile, args->max_y_tile,
616 exec->bin_tiles_x, exec->bin_tiles_y);
617 return -EINVAL;
618 }
619
620 ret = vc4_rcl_render_config_surface_setup(exec, &setup,
621 &setup.color_write,
622 &args->color_write);
623 if (ret)
624 return ret;
625
626 ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read,
627 false);
628 if (ret)
629 return ret;
630
631 ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read,
632 false);
633 if (ret)
634 return ret;
635
636 ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write,
637 true);
638 if (ret)
639 return ret;
640
641 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write,
642 &args->msaa_color_write);
643 if (ret)
644 return ret;
645
646 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write,
647 &args->msaa_zs_write);
648 if (ret)
649 return ret;
650
651 /* We shouldn't even have the job submitted to us if there's no
652 * surface to write out.
653 */
654 if (!setup.color_write && !setup.zs_write &&
655 !setup.msaa_color_write && !setup.msaa_zs_write) {
656 DRM_DEBUG("RCL requires color or Z/S write\n");
657 return -EINVAL;
658 }
659
660 return vc4_create_rcl_bo(dev, exec, &setup);
661 }
662
