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Searched refs:tegra_dc_writel (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/tegra/
Ddc.c42 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
111 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
868 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
872 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
878 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
887 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
891 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
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Drgb.c87 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
147 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
153 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
158 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
162 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_rgb_encoder_enable()
Dhub.c95 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
174 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_update()
194 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_activate()
266 tegra_dc_writel(dc, value, offset); in tegra_shared_plane_set_owner()
667 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL); in tegra_display_hub_update()
671 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); in tegra_display_hub_update()
673 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
675 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
Dhdmi.c1209 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1275 tegra_dc_writel(dc, VSYNC_H_POSITION(1), in tegra_hdmi_encoder_enable()
1277 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, in tegra_hdmi_encoder_enable()
1283 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_hdmi_encoder_enable()
1287 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_hdmi_encoder_enable()
1290 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_hdmi_encoder_enable()
1428 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()
Dsor.c1535 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1891 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
2184 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2387 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2390 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2394 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2484 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2514 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2559 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2565 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
Ddc.h111 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, in tegra_dc_writel() function
Ddsi.c867 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
934 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()